Rockwell Automation SD3000 Drive Configuration, Programming User Manual
Page 36
1 00/1 100
Drive Control Register (Continued)
Bit: 7
Hex Value: 0080H
Sug. Var. Name:
FML_ATR@
Range:
N/A
Access:
Read/Write
UDC Error Code:
N/A
LED:
N/A
Description:
The Field Alpha Test Polarity bit is set to select the reverse bridge for the field alpha
test. Bit 6 must also be set. The firing angle value is entered into the Field Test Angle register
104/1 104 (FLD_ALPHA%). This test is for the single phase field only. If this bit is not set the forward
bridge will be tested.
Bit: 8
Hex Value:
01 00H
Sug. Var. Name:
FLT_RST@
Range:
N/A
Access:
Read/Write
UDC Error Code:
N/A
LED:
N/A
Description:
The Fault Reset bit is set and reset to clear the Drive Fault register 202/1 202. After a
drive fault is latched, the Drive Fault register must be cleared before the drive can be re-started. First,
any command bits that have been set in the Drive Control register (100/1 100) must be turned off.
Once the cause of the fault has been corrected, the Fault Reset bit must be turned on and then off
again. The Fault Reset bit will clear the entire Drive Fault register. Then the desired command bits
may be turned on again.
The Fault Reset bit is edge-sensitive, i.e., leaving it set will not clear the Drive Fault register continu-
ously. Note that if the fault condition still exists after register 202/1 202 is cleared, it will continue to
trigger drive faults until the problem has been corrected.
Bit: 9
Hex Value: 0200H
Sug. Var. Name:
WRN_RST@
Range:
N/A
Access:
Read/Write
UDC Error Code:
N/A
LED:
N/A
Description:
The Warning Reset bit is set and reset to clear the Drive Warning register 203/1 203.
This bit is edge-sensitive, i.e., leaving it on will not clear the warning register continuously. The Inter-
lock register (205/1205) is also cleared by setting and then resetting the Warning Reset bit.
Bit: 11
Hex Value: 0800H
Sug. Var. Name:
NO_FLDW@
Range:
N/A
Access:
Read/Write
UDC Error Code:
N/A
LED:
N/A
Description:
Automatic field weakening defaults to being on. When field weakening is enabled and
the CEMF value is greater than the motor voltage minus the rated IR drop, the field will automatically
be weakened in order to maintain constant CEME This maintains CEMF at its maximum value, which
is found at motor base speed. The field control algorithm uses the smaller of the following values,
either the value entered into the Field Current Reference register (105/1105) or the algorithm
calculated value designed to keep CEMF constant.
The Disable Field Weakening bit is set to disable automatic field weakening. When automatic field
weakening is disabled, the programmer has exclusive control over the field current reference value.
This does not mean that field weakening cannot be done, only that field weakening will not be done
automatically by the field control algorithm. The programmer must provide the proper field control
reference value.
Refer to Appendix H for more information. The figure shows the field current regulation algorithm with
field weakening disabled.
Note that if the programmer selects No Speed Feedback during parameter entry, automatic field
weakening will be disabled and the status of the Disable Field Weakening bit will be ignored by the
PMI OS.