Document Outline

• MSP430x4xx - SLAU056E
• IMPORTANT NOTICE
• Read This First
  • About This Manual
  • Related Documentation From Texas Instruments
  • FCC Warning
  • Notational Conventions
  • Glossary
  • Register Bit Conventions
• Contents
• Chapter 1: Introduction
  • 1.1 Architecture
  • 1.2 Flexible Clock System
  • 1.3 Embedded Emulation
  • 1.4 Address Space
    • 1.4.1 Flash/ROM
    • 1.4.2 RAM
    • 1.4.3 Peripheral Modules
    • 1.4.4 Special Function Registers (SFRs)
    • 1.4.5 Memory Organization
• Chapter 2: System Resets, Interrupts, and Operating Modes
  • 2.1 System Reset and Initialization
    • 2.1.1 Brownout Reset (BOR)
    • 2.1.2 Device Initial Conditions After System Reset
      • Software Initialization
  • 2.2 Interrupts
    • 2.2.1 (Non)-Maskable Interrupts (NMI)
      • Reset/NMI Pin
      • Oscillator Fault
      • Flash Access Violation
      • Example of an NMI Interrupt Handler
    • 2.2.2 Maskable Interrupts
    • 2.2.3 Interrupt Processing
      • Interrupt Acceptance
      • Return From Interrupt
    • 2.2.4 Interrupt Vectors
    • 2.2.5 Special Function Registers (SFRs)
  • 2.3 Operating Modes
    • 2.3.1 Entering and Exiting Low-Power Modes
      • Extended Time in Low-Power Modes
  • 2.4 Principles for Low-Power Applications
  • 2.5 Connection of Unused Pins
• Chapter 3: RISC 16-Bit CPU
  • 3.1 CPU Introduction
  • 3.2 CPU Registers
    • 3.2.1 Program Counter (PC)
    • 3.2.2 Stack Pointer (SP)
    • 3.2.3 Status Register (SR)
    • 3.2.4 Constant Generator Registers CG1 and CG2
      • Constant Generator - Expanded Instruction Set
    • 3.2.5 General-Purpose Registers R4 - R15
  • 3.3 Addressing Modes
    • 3.3.1 Register Mode
    • 3.3.2 Indexed Mode
    • 3.3.3 Symbolic Mode
    • 3.3.4 Absolute Mode
    • 3.3.5 Indirect Register Mode
    • 3.3.6 Indirect Autoincrement Mode
    • 3.3.7 Immediate Mode
  • 3.4 Instruction Set
    • 3.4.1 Double-Operand (Format I) Instructions
    • 3.4.2 Single-Operand (Format II) Instructions
    • 3.4.3 Jumps
    • 3.4.4 Instruction Cycles and Lengths
      • Interrupt and Reset Cycles
      • Format-II (Single Operand) Instruction Cycles and Lengths
      • Format-III (Jump) Instruction Cycles and Lengths
      • Format-I (Double Operand) Instruction Cycles and Lengths
    • 3.4.5 Instruction Set Description
• Chapter 4: FLL+ Clock Module
  • 4.1 FLL+ Clock Module Introduction
  • 4.2 FLL+ Clock Module Operation
    • 4.2.1 FLL+ Clock features for Low-Power Applications
    • 4.2.2 LFXT1 Oscillator
    • 4.2.3 XT2 Oscillator
    • 4.2.4 Digitally-Controlled Oscillator (DCO)
      • DCO Frequency Range
    • 4.2.5 Frequency Locked Loop (FLL)
    • 4.2.6 DCO Modulator
    • 4.2.7 Disabling the FLL Hardware and Modulator
    • 4.2.8 FLL Operation from Low-Power Modes-
    • 4.2.9 Buffered Clock Output
    • 4.2.10 FLL+ Fail-Safe Operation
  • 4.3 FLL+ Clock Module Registers
    • SCFQCTL, System Clock Control Register
    • SCFI0, System Clock Frequency Integrator Register 0
    • SCFI1, System Clock Frequency Integrator Register 1
    • FLL_CTL0, FLL+ Control Register 0
    • FLL_CTL1, FLL+ Control Register 1
    • IE1, Interrupt Enable Register 1
    • IFG1, Interrupt Flag Register 1
• Chapter 5: Flash Memory Controller
  • 5.1 Flash Memory Introduction
  • 5.2 Flash Memory Segmentation
  • 5.3 Flash Memory Operation
    • 5.3.1 Flash Memory Timing Generator
    • 5.3.2 Erasing Flash Memory
      • Initiating an Erase from Within Flash Memory
      • Initiating an Erase from RAM
    • 5.3.3 Writing Flash Memory
      • Byte/Word Write
      • Initiating a Byte/Word Write from Within Flash Memory
      • Initiating a Byte/Word Write from RAM
      • Block Write
      • Block Write Flow and Example
    • 5.3.4 Flash Memory Access During Write or Erase
    • 5.3.5 Stopping a Write or Erase Cycle
    • 5.3.6 Configuring and Accessing the Flash Memory Controller
    • 5.3.7 Flash Memory Controller Interrupts
    • 5.3.8 Programming Flash Memory Devices
      • Programming Flash Memory via JTAG
      • Programming Flash Memory via the Bootstrap loader (BSL)
      • Programming Flash Memory via a Custom Solution
  • 5.4 Flash Memory Registers
    • FCTL1, Flash Memory Control Register
    • FCTL2, Flash Memory Control Register
    • FCTL3, Flash Memory Control Register FCTL3
    • IE1, Interrupt Enable Register 1
• Chapter 6: Supply Voltage Supervisor
  • 6.1 SVS Introduction
  • 6.2 SVS Operation
    • 6.2.1 Configuring the SVS
    • 6.2.2 SVS Comparator Operation
    • 6.2.3 Changing the VLDx Bits
    • 6.2.4 SVS Operating Range
  • 6.3 SVS Registers
    • SVSCTL, SVS Control Register
• Chapter 7: Hardware Multiplier
  • 7.1 Hardware Multiplier Introduction
  • 7.2 Hardware Multiplier Operation
    • 7.2.1 Operand Registers
    • 7.2.2 Result Registers
      • MACS Underflow and Overflow
    • 7.2.3 Software Examples
    • 7.2.4 Indirect Addressing of RESLO
    • 7.2.5 Using Interrupts
  • 7.3 Hardware Multiplier Registers
• Chapter 8: DMA Controller
  • 8.1 DMA Introduction
  • 8.2 DMA Operation
    • 8.2.1 DMA Addressing Modes
    • 8.2.2 DMA Transfer Modes
      • Single Transfer
      • Block Transfers
      • Burst-Block Transfers
    • 8.2.3 Initiating DMA Transfers
      • Edge-Sensitive Triggers
      • Level-Sensitive Triggers
      • Halting Executing Instructions for DMA Transfers
    • 8.2.4 Stopping DMA Transfers
    • 8.2.5 DMA Channel Priorities
    • 8.2.6 DMA Transfer Cycle Time
    • 8.2.7 Using DMA with System Interrupts
    • 8.2.8 DMA Controller Interrupts
    • 8.2.9 Using the I2C Module with the DMA Controller
    • 8.2.10 Using ADC12 with the DMA Controller
    • 8.2.11 Using DAC12 With the DMA Controller
  • 8.3 DMA Registers
    • DMACTL0, DMA Control Register 0
    • DMACTL1, DMA Control Register 1
    • DMAxCTL, DMA Channel x Control Register
    • DMAxSA, DMA Source Address Register
    • DMAxDA, DMA Destination Address Register
    • DMAxSZ, DMA Size Address Register
• Chapter 9: Digital I/O
  • 9.1 Digital I/O Introduction
  • 9.2 Digital I/O Operation
    • 9.2.1 Input Register PxIN
    • 9.2.2 Output Registers PxOUT
    • 9.2.3 Direction Registers PxDIR
    • 9.2.4 Function Select Registers PxSEL
    • 9.2.5 P1 and P2 Interrupts
      • Interrupt Flag Registers P1IFG, P2IFG
      • Interrupt Edge Select Registers P1IES, P2IES
      • Interrupt Enable P1IE, P2IE
    • 9.2.6 Configuring Unused Port Pins
  • 9.3 Digital I/O Registers
• Chapter 10: Watchdog Timer, Watchdog Timer+
  • 10.1 Watchdog Timer Introduction
  • 10.2 Watchdog Timer Operation
    • 10.2.1 Watchdog Timer Counter
    • 10.2.2 Watchdog Mode
    • 10.2.3 Interval Timer Mode
    • 10.2.4 Watchdog Timer Interrupts
    • 10.2.5 WDT+ Enhancements
    • 10.2.6 Operation in Low-Power Modes
    • 10.2.7 Software Examples
  • 10.3 Watchdog Timer Registers
    • WDTCTL, Watchdog Timer Register
    • IE1, Interrupt Enable Register 1
    • IFG1, Interrupt Flag Register 1
• Chapter 11: Basic Timer1
  • 11.1 Basic Timer1 Introduction
  • 11.2 Basic Timer1 Operation
    • 11.2.1 Basic Timer1 Counter One
    • 11.2.2 Basic Timer1 Counter Two
    • 11.2.3 16-bit Counter Mode
    • 11.2.4 Basic Timer1 Operation: Signal fLCD
    • 11.2.5 Basic Timer1 Interrupts
  • 11.3 Basic Timer1 Registers
    • BTCTL, Basic Timer1 Control Register
    • BTCNT1, Basic Timer1 Counter 1
    • BTCNT2, Basic Timer1 Counter 2
    • IE2, Interrupt Enable Register 2
    • IFG2, Interrupt Flag Register 2
• Chapter 12: Timer_A
  • 12.1 Timer_A Introduction
  • 12.2 Timer_A Operation
    • 12.2.1 16-Bit Timer Counter
      • Clock Source Select and Divider
    • 12.2.2 Starting the Timer
    • 12.2.3 Timer Mode Control
      • Up Mode
        • Changing the Period Register TACCR0
      • Continuous Mode
        • Use of the Continuous Mode
      • Up/Down Mode
        • Changing the Period Register TACCR0
        • Use of the Up/Down Mode
    • 12.2.4 Capture/Compare Blocks
      • Capture Mode
        • Capture Initiated by Software
      • Compare Mode
    • 12.2.5 Output Unit
      • Output Modes
        • Output Example—Timer in Up Mode
        • Output Example—Timer in Continuous Mode
        • Output Example—Timer in Up/Down Mode
    • 12.2.6 Timer_A Interrupts
      • TACCR0 Interrupt
      • TAIV, Interrupt Vector Generator
        • TAIV Software Example
  • 12.3 Timer_A Registers
    • TACTL, Timer_A Control Register
    • TAR, Timer_A Register
    • TACCTLx, Capture/Compare Control Register
    • TAIV, Timer_A Interrupt Vector Register
• Chapter 13: Timer_B
  • 13.1 Timer_B Introduction
    • 13.1.1 Similarities and Differences From Timer_A
  • 13.2 Timer_B Operation
    • 13.2.1 16-Bit Timer Counter
      • TBR Length
      • Clock Source Select and Divider
    • 13.2.2 Starting the Timer
    • 13.2.3 Timer Mode Control
      • Up Mode
        • Changing the Period Register TBCL0
      • Continuous Mode
        • Use of the Continuous Mode
      • Up/Down Mode
        • Changing the Value of Period Register TBCL0
        • Use of the Up/Down Mode
    • 13.2.4 Capture/Compare Blocks
      • Capture Mode
        • Capture Initiated by Software
      • Compare Mode
        • Compare Latch TBCLx
        • Grouping Compare Latches
    • 13.2.5 Output Unit
      • Output Modes
        • Output Example—Timer in Up Mode
        • Output Example—Timer in Continuous Mode
        • Output Example - Timer in Up/Down Mode
    • 13.2.6 Timer_B Interrupts
      • TBCCR0 Interrupt Vector
      • TBIV, Interrupt Vector Generator
      • TBIV, Interrupt Handler Examples
  • 13.3 Timer_B Registers
    • Timer_B Control Register TBCTL
    • TBR, Timer_B Register
    • TBCCTLx, Capture/Compare Control Register
    • TBIV, Timer_B Interrupt Vector Register
• Chapter 14: USART Peripheral Interface, UART Mode
  • 14.1 USART Introduction: UART Mode
  • 14.2 USART Operation: UART Mode
    • 14.2.1 USART Initialization and Reset
    • 14.2.2 Character Format
    • 14.2.3 Asynchronous Communication Formats
      • Idle-Line Multiprocessor Format
      • Address-Bit Multiprocessor Format
      • Automatic Error Detection
    • 14.2.4 USART Receive Enable
    • 14.2.5 USART Transmit Enable
    • 14.2.6 UART Baud Rate Generation
      • Baud Rate Bit Timing
      • Determining the Modulation Value
      • Transmit Bit Timing
      • Receive Bit Timing
      • Typical Baud Rates and Errors
    • 14.2.7 USART Interrupts
      • USART Transmit Interrupt Operation
      • USART Receive Interrupt Operation
      • Receive-Start Edge Detect Operation
        • Receive-Start Edge Detect Conditions
  • 14.3 USART Registers: UART Mode
    • UxCTL, USART Control Register
    • UxTCTL, USART Transmit Control Register
    • UxRCTL, USART Receive Control Register
    • UxBR0, USART Baud Rate Control Register 0
    • UxBR1, USART Baud Rate Control Register 1
    • UxMCTL, USART Modulation Control Register
    • UxRXBUF, USART Receive Buffer Register
    • UxTXBUF, USART Transmit Buffer Register
    • ME1, Module Enable Register 1
    • ME2, Module Enable Register 2
    • IE1, Interrupt Enable Register 1
    • IE2, Interrupt Enable Register 2
    • IFG1, Interrupt Flag Register 1
    • IFG2, Interrupt Flag Register 2
• Chapter 15: UASRT Peripheral Interface, SPI Mode
  • 15.1 USART Introduction: SPI Mode
  • 15.2 USART Operation: SPI Mode
    • 15.2.1 USART Initialization and Reset
    • 15.2.2 Master Mode
      • Four-Pin SPI Master Mode
    • 15.2.3 Slave Mode
      • Four-Pin SPI Slave Mode
    • 15.2.4 SPI Enable
      • Transmit Enable
      • Receive Enable
    • 15.2.5 Serial Clock Control
      • Serial Clock Polarity and Phase
    • 15.2.6 SPI Interrupts
      • SPI Transmit Interrupt Operation
      • SPI Receive Interrupt Operation
  • 15.3 USART Registers: SPI Mode
    • UxCTL, USART Control Register
    • UxTCTL, USART Transmit Control Register
    • UxRCTL, USART Receive Control Register
    • UxBR0, USART Baud Rate Control Register 0
    • UxBR1, USART Baud Rate Control Register 1
    • UxMCTL, USART Modulation Control Register
    • UxRXBUF, USART Receive Buffer Register
    • UxTXBUF, USART Transmit Buffer Register
    • ME1, Module Enable Register 1
    • ME2, Module Enable Register 2
    • IE1, Interrupt Enable Register 1
    • IE2, Interrupt Enable Register 2
    • IFG1, Interrupt Flag Register 1
    • IFG2, Interrupt Flag Register 2
• Chapter 16: OA
  • 16.1 OA Introduction
  • 16.2 OA Operation
    • 16.2.1 OA Amplifier
    • 16.2.2 OA Input
    • 16.2.3 OA Output
    • 16.2.4 OA Configurations
      • General Purpose Opamp Mode
      • Unity Gain Mode
      • Comparator Mode
      • Non-Inverting PGA Mode
      • Inverting PGA Mode
      • Differential Amplifier Mode
  • 16.3 OA Registers
    • OAxCTL0, Opamp Control Register 0
    • OAxCTL1, Opamp Control Register 1
• Chapter 17: Comparator_A
  • 17.1 Comparator_A Introduction
  • 17.2 Comparator_A Operation
    • 17.2.1 Comparator
    • 17.2.2 Input Analog Switches
    • 17.2.3 Output Filter
    • 17.2.4 Voltage Reference Generator
    • 17.2.5 Comparator_A, Port Disable Register CAPD
    • 17.2.6 Comparator_A Interrupts
    • 17.2.7 Comparator_A Used to Measure Resistive Elements
  • 17.3 Comparator_A Registers
    • CACTL1, Comparator_A Control Register 1
    • CACTL2, Comparator_A Control Register 2
    • CAPD, Comparator_A Port Disable Register
• Chapter 18: LCD Controller
  • 18.1 LCD Controller Introduction
  • 18.2 LCD Controller Operation
    • 18.2.1 LCD Memory
    • 18.2.2 Blinking the LCD
    • 18.2.3 LCD Timing Generation
    • 18.2.4 LCD Voltage Generation
      • LCD Contrast Control
    • 18.2.5 LCD Outputs
    • 18.2.6 Static Mode
      • Static Mode Software Example
    • 18.2.7 2-Mux Mode
      • 2-Mux Mode Software Example
    • 18.2.8 3-Mux Mode
      • 3-Mux Mode Software Example
    • 18.2.9 4-Mux Mode
      • 4-Mux Mode Software Example
  • 18.3 LCD Controller Registers
    • LCDCTL, LCD Control Register
• Chapter 19: LCD_A Controller
  • 19.1 LCD_A Controller Introduction
  • 19.2 LCD_A Controller Operation
    • 19.2.1 LCD Memory
    • 19.2.2 Blinking the LCD
    • 19.2.3 LCD_A Voltage And Bias Generation
      • LCD Voltage Selection
      • LCD Bias Generation
      • LCD Contrast Control
    • 19.2.4 LCD Timing Generation
    • 19.2.5 LCD Outputs
    • 19.2.6 Static Mode
      • Static Mode Software Example
    • 19.2.7 2-Mux Mode
      • 2-Mux Mode Software Example
    • 19.2.8 3-Mux Mode
      • 3-Mux Mode Software Example
    • 19.2.9 4-Mux Mode
      • 4-Mux Mode Software Example
  • 19.3 LCD Controller Registers
    • LCDACTL, LCD_A Control Register
    • LCDAPCTL0, LCD_A Port Control Register 0
    • LCDAPCTL1, LCD_A Port Control Register 1
    • LCDAVCTL0, LCD_A Voltage Control Register 0
    • LCDAVCTL1, LCD_A Voltage Control Register 1
• Chapter 20: ADC12
  • 20.1 ADC12 Introduction
  • 20.2 ADC12 Operation
    • 20.2.1 12-Bit ADC Core
      • Conversion Clock Selection
    • 20.2.2 ADC12 Inputs and Multiplexer
      • Analog Port Selection
    • 20.2.3 Voltage Reference Generator
    • 20.2.4 Auto Power-Down
    • 20.2.5 Sample and Conversion Timing
      • Extended Sample Mode
      • Pulse Sample Mode
      • Sample Timing Considerations
    • 20.2.6 Conversion Memory
    • 20.2.7 ADC12 Conversion Modes
      • Single-Channel Single-Conversion Mode
      • Sequence-of-Channels Mode
      • Repeat-Single-Channel Mode
      • Repeat-Sequence-of-Channels Mode
      • Using the Multiple Sample and Convert (MSC) Bit
      • Stopping Conversions
    • 20.2.8 Using the Integrated Temperature Sensor
    • 20.2.9 ADC12 Grounding and Noise Considerations
    • 20.2.10 ADC12 Interrupts
      • ADC12IV, Interrupt Vector Generator
      • ADC12 Interrupt Handling Software Example
  • 20.3 ADC12 Registers
    • ADC12CTL0, ADC12 Control Register 0
    • ADC12CTL1, ADC12 Control Register 1
    • ADC12MEMx, ADC12 Conversion Memory Registers
    • ADC12MCTLx, ADC12 Conversion Memory Control Registers
    • ADC12IE, ADC12 Interrupt Enable Register
    • ADC12IFG, ADC12 Interrupt Flag Register
    • ADC12IV, ADC12 Interrupt Vector Register
• Chapter 21: SD16
  • 21.1 SD16 Introduction
  • 21.2 SD16 Operation
    • 21.2.1 ADC Core
    • 21.2.2 Analog Input Range and PGA
    • 21.2.3 Voltage Reference Generator
    • 21.2.4 Auto Power-Down
    • 21.2.5 Channel Selection
      • Analog Input Setup
      • Analog Input Characteristics
      • Anti-Aliasing Filter
    • 21.2.6 Digital Filter
      • Digital Filter Output
    • 21.2.7 Conversion Memory Registers: SD16MEMx
      • Output Data Format
    • 21.2.8 Conversion Modes
      • Single Channel, Single Conversion
      • Single Channel, Continuous Conversion
      • Group of Channels, Single Conversion
      • Group of Channels, Continuous Conversion
    • 21.2.9 Conversion Operation Using Preload
    • 21.2.10 Using the Integrated Temperature Sensor
    • 21.2.11 Interrupt Handling
      • SD16IV, Interrupt Vector Generator
      • Interrupt Delay Operation
      • SD16 Interrupt Handling Software Example
  • 21.3 SD16 Registers
    • SD16CTL, SD16 Control Register
    • SD16CCTLx, SD16 Channel x Control Register
    • SD16INCTLx, SD16 Channel x Input Control Register
    • SD16MEMx, SD16 Channel x Conversion Memory Register
    • SD16PREx, SD16 Channel x Preload Register
    • SD16IV, SD16 Interrupt Vector Register
• Chapter 22: SD16_A
  • 22.1 SD16_A Introduction
  • 22.2 SD16_A Operation
    • 22.2.1 ADC Core
    • 22.2.2 Analog Input Range and PGA
    • 22.2.3 Voltage Reference Generator
    • 22.2.4 Auto Power-Down
    • 22.2.5 Channel Selection
      • Analog Input Setup
    • 22.2.6 Analog Input Characteristics
    • 22.2.7 Digital Filter
      • Digital Filter Output
    • 22.2.8 Conversion Memory Register: SD16MEM0
      • Output Data Format
    • 22.2.9 Conversion Modes
      • Single Conversion
      • Continuous Conversion
    • 22.2.10 Using the Integrated Temperature Sensor
    • 22.2.11 Interrupt Handling
      • SD16IV, Interrupt Vector Generator
      • Interrupt Delay Operation
  • 22.3 SD16_A Registers
    • SD16CTL, SD16_A Control Register
    • SD16CCTL0, SD16_A Control Register 0
    • SD16INCTL0, SD16_A Input Control Register
    • SD16MEM0, SD16_A Conversion Memory Register
    • SD16AE, SD16_A Analog Input Enable Register
    • SD16IV, SD16_A Interrupt Vector Register
• Chapter 23: DAC12
  • 23.1 DAC12 Introduction
  • 23.2 DAC12 Operation
    • 23.2.1 DAC12 Core
      • DAC12 Port Selection
    • 23.2.2 DAC12 Reference
      • DAC12 Reference Input and Voltage Output Buffers
    • 23.2.3 Updating the DAC12 Voltage Output
    • 23.2.4 DAC12_xDAT Data Format
    • 23.2.5 DAC12 Output Amplifier Offset Calibration
    • 23.2.6 Grouping Multiple DAC12 Modules
    • 23.2.7 DAC12 Interrupts
  • 23.3 DAC12 Registers
    • DAC12_xCTL, DAC12 Control Register
    • DAC12_xDAT, DAC12 Data Register
• Chapter 24: Scan IF
  • 24.1 Scan IF Introduction
  • 24.2 Scan IF Operation
    • 24.2.1 Scan IF Analog Front End
      • Excitation
      • Mid-Voltage Generator
      • Sample-And-Hold
      • Direct Analog And Digital Inputs
      • Comparator Input Selection And Output Bit Selection
      • Internal Signal Connections to Timer1_A5
    • 24.2.2 Scan IF Timing State Machine
      • TSM Operation
      • TSM Control of the AFE
      • TSM State Duration
      • TSM State Clock Source Select
      • TSM Stop Condition
      • TSM Test Cycles
      • TSM Example
    • 24.2.3 Scan IF Processing State Machine
      • PSM Operation
      • Next State Calculation
      • PSM Counters
      • Simplest State Machine
    • 24.2.4 Scan IF Debug Register
    • 24.2.5 Scan IF Interrupts
    • 24.2.6 Using the Scan IF with LC Sensors
      • 24.2.6.1 LC-Sensor Oscillation Test
      • 24.2.6.2 LC-Sensor Envelope Test
    • 24.2.7 Using the Scan IF With Resistive Sensors
    • 24.2.8 Quadrature Decoding
  • 24.3 Scan IF Registers
    • SIFDEBUG, Scan IF Debug Register, Write Mode
    • SIFDEBUG, Scan IF Debug Register, Read Mode After 00h Is Written
    • SIFDEBUG, Scan IF Debug Register, Read Mode After 01h Is Written
    • SIFDEBUG, Scan IF Debug Register, Read Mode After 02h Is Written
    • SIFDEBUG, Scan IF Debug Register, Read Mode After 03h Is Written
    • SIFCNT, Scan IF Counter Register
    • SIFPSMV, Scan IF Processing State Machine Vector Register
    • SIFCTL1, Scan IF Control Register 1
    • SIFCTL2, Scan IF Control Register 2
    • SIFCTL3, Scan IF Control Register 3
    • SIFCTL4, Scan IF Control Register 4
    • SIFCTL5, Scan IF Control Register 5
    • SIFDACRx, Digital-To-Analog Converter Registers
    • SIFTSMx, Scan IF Timing State Machine Registers
    • Processing State Machine Table Entry (MSP430 Memory Location)