Texas Instruments MSP430x4xx - Manual (Page 218)

Timer_A Operation
12-9 Timer_A
Up/Down Mode
The up/down mode is used if the timer period must be different from 0FFFFh
counts, and if symmetrical pulse generation is needed. The timer repeatedly
counts up to the value of compare register TACCR0 and back down to zero,
as shown in Figure 12−7. The period is twice the value in TACCR0.
Figure 12−7. Up/Down Mode
0h
TACCR0
0FFFFh
The count direction is latched. This allows the timer to be stopped and then
restarted in the same direction it was counting before it was stopped. If this is
not desired, the TACLR bit must be set to clear the direction. The TACLR bit
also clears the TAR value and the TACLK divider.
In up/down mode, the TACCR0 CCIFG interrupt flag and the TAIFG interrupt
flag are set only once during a period, separated by 1/2 the timer period. The
TACCR0 CCIFG interrupt flag is set when the timer counts from TACCR0−1
to TACCR0, and TAIFG is set when the timer completes counting down from
0001h to 0000h. Figure 12−8 shows the flag set cycle.
Figure 12−8. Up/Down Mode Flag Setting
CCR0−1 CCR0 CCR0−1
Timer Clock
Timer
Set TAIFG
Set TACCR0 CCIFG
CCR0−2 1h 0h
Up/Down