1 fll+ clock module introduction – Texas Instruments MSP430x4xx User Manual

Page 111

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4-2

FLL+ Clock Module

4.1

FLL+ Clock Module Introduction

The frequency-locked loop (FLL+) clock module supports low system cost and
ultralow-power consumption. Using three internal clock signals, the user can
select the best balance of performance and low power consumption. The FLL+
features digital frequency-locked loop (FLL) hardware. The FLL operates
together with a digital modulator and stabilizes the internal digitally controlled
oscillator (DCO) frequency to a programmable multiple of the LFXT1 watch
crystal frequency. The FLL+ clock module can be configured to operate
without any external components, with one or two external crystals, or with
resonators, under full software control.

The FLL+ clock module includes two or three clock sources:

-

LFXT1CLK: Low-frequency/high-frequency oscillator that can be used
either with low-frequency 32768-Hz watch crystals, or standard crystals
or resonators in the 450-kHz to 8-MHz range.

-

XT2CLK: Optional high-frequency oscillator that can be used with
standard crystals, resonators, or external clock sources in the 450-kHz to
8-MHz range.

-

DCOCLK: Internal digitally controlled oscillator (DCO) with RC-type
characteristics, stabilized by the FLL.

-

Four clock signals are available from the FLL+ module:

-

ACLK: Auxiliary clock. The ACLK is the LFXT1CLK clock source. ACLK
is software selectable for individual peripheral modules.

-

ACLK/n: Buffered output of the ACLK. The ACLK/n is ACLK divided by
1,2,4 or 8 and only used externally.

-

MCLK: Master clock. MCLK is software selectable as LFXT1CLK,
XT2CLK (if available), or DCOCLK. MCLK can be divided by 1, 2, 4, or 8
within the FLL block. MCLK is used by the CPU and system.

-

SMCLK: Sub-main clock. SMCLK is software selectable as XT2CLK (if
available), or DCOCLK. SMCLK is software selectable for individual
peripheral modules.

The block diagram of the FLL+ clock module is shown in Figure 4−1 for the
MSP430x44x and MSP430x43x. The block diagram of the FLL+ clock module
is shown in Figure 4−2 for the MSP430x42x and MSP430x41x.

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