Sifcnt, scan if counter register – Texas Instruments MSP430x4xx User Manual
Page 499
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Scan IF Registers
24-39
Scan IF
SIFCNT, Scan IF Counter Register
15
14
13
12
11
10
9
8
SIFCNT2x
r−(0)
r−(0)
r−(0)
r−(0)
r−(0)
r−(0)
r−(0)
r−(0)
7
6
5
4
3
2
1
0
SIFCNT1x
r−(0)
r−(0)
r−(0)
r−(0)
r−(0)
r−(0)
r−(0)
r−(0)
SIFCNT2x
Bits
15-8
SIFCNT2. These bits are the SIFCNT2 counter. SIFCNT2 is reset when
SIFEN = 0 or if read when SIFCNTRST = 1.
SIFCNT1x
Bits
7-0
SIFCNT1. These bits are the SIFCNT1 counter. SIFCNT1 is reset when
SIFEN = 0 or if read when SIFCNTRST = 1.
SIFPSMV, Scan IF Processing State Machine Vector Register
15
14
13
12
11
10
9
8
SIFPSMVx
rw−(0)
rw−(0)
rw−(0)
rw−(0)
rw−(0)
rw−(0)
rw−(0)
rw−(0)
7
6
5
4
3
2
1
0
SIFPSMVx
rw−(0)
rw−(0)
rw−(0)
rw−(0)
rw−(0)
rw−(0)
rw−(0)
rw−(0)
SIFPSMVx
Bits
15-0
SIF PSM vector. These bits are the address for the first state in the PSM state
table.
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