Texas Instruments MSP430x4xx User Manual
Page 272
USART Operation: UART Mode
14-15
USART Peripheral Interface, UART Mode
For example, the receive errors for the following conditions are calculated:
Baud rate = 2400
BRCLK =
32,768 Hz (ACLK)
UxBR =
13, since the ideal division factor is 13.65
UxMCTL =
6B:m7=0, m6 =1, m5 =1, m4 =0, m3 =1, m2 =0, m1 =1 and
m0=1 The LSB of UxMCTL is used first.
Data bit D1 Error [%]
+
ǒ
baud rate
BRCLK
[2x(1
)
6)
)
(2
UxBR
)
1)]–1–2
Ǔ
100%
+
0.29%
Data bit D2 Error [%]
+
ǒ
baud rate
BRCLK
[2x(1
)
6)
)
(3
UxBR
)
2)]–1–3
Ǔ
100%
+
2.83%
Data bit D3 Error [%]
+
ǒ
baud rate
BRCLK
[2x(1
)
6)
)
(4
UxBR
)
2)]–1–4
Ǔ
100%
+
–1.95%
Data bit D4 Error [%]
+
ǒ
baud rate
BRCLK
[2x(1
)
6)
)
(5
UxBR
)
3)]–1–5
Ǔ
100%
+
0.59%
Data bit D5 Error [%]
+
ǒ
baud rate
BRCLK
[2x(1
)
6)
)
(6
UxBR
)
4)]–1–6
Ǔ
100%
+
3.13%
Data bit D6 Error [%]
+
ǒ
baud rate
BRCLK
[2x(1
)
6)
)
(7
UxBR
)
4)]–1–7
Ǔ
100%
+
–1.66%
Data bit D7 Error [%]
+
ǒ
baud rate
BRCLK
[2x(1
)
6)
)
(8
UxBR
)
5)]–1–8
Ǔ
100%
+
0.88%
Parity bit Error [%]
+
ǒ
baud rate
BRCLK
[2x(1
)
6)
)
(9
UxBR
)
6)]–1–9
Ǔ
100%
+
3.42%
Stop bit 1 Error [%]
+
ǒ
baud rate
BRCLK
[2x(1
)
6)
)
(10
UxBR
)
6)]–1–10
Ǔ
100%
+
–1.37%
Start bit Error [%]
+
ǒ
baud rate
BRCLK
[2x(1
)
6)
)
(0
UxBR
)
0)]
*
1
*
0
Ǔ
100%
+
2.54%
Data bit D0 Error [%]
+
ǒ
baud rate
BRCLK
[2x(1
)
6)
)
(1
UxBR
)
1)]–1–1
Ǔ
100%
+
5.08%
The results show the maximum per-bit error to be 5.08% of a BITCLK period.