Texas Instruments MSP430x4xx - Manual (Page 70)

Instruction Set
3-36 RISC 16−Bit CPU
DADD[.W] Source and carry added decimally to destination
DADD.B Source and carry added decimally to destination
Syntax DADD src,dst or DADD.W src,dst
DADD.B src,dst
Operation src + dst + C −> dst (decimally)
Description The source operand and the destination operand are treated as four binary
coded decimals (BCD) with positive signs. The source operand and the carry
bit (C) are added decimally to the destination operand. The source operand
is not affected. The previous contents of the destination are lost. The result is
not defined for non-BCD numbers.
Status Bits N: Set if the MSB is 1, reset otherwise
Z: Set if result is zero, reset otherwise
C: Set if the result is greater than 9999
Set if the result is greater than 99
V: Undefined
Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Example The eight-digit BCD number contained in R5 and R6 is added decimally to an
eight-digit BCD number contained in R3 and R4 (R6 and R4 contain the
MSDs).
CLRC ; clear carry
DADD R5,R3 ; add LSDs
DADD R6,R4 ; add MSDs with carry
JC OVERFLOW ; If carry occurs go to error handling routine
Example The two-digit decimal counter in the RAM byte CNT is incremented by one.
CLRC ; clear carry
DADD.B #1,CNT ; increment decimal counter
or
SETC
DADD.B
#0,CNT ;
≡
DADC.B CNT