Texas Instruments MSP430x4xx - Manual (Page 419)

SD16 Operation
21-16 SD16
21.2.11 Interrupt Handling
The SD16 has 2 interrupt sources for each ADC channel:
- SD16IFG
- SD16OVIFG
The SD16IFG bits are set when their corresponding SD16MEMx memory
register is written with a conversion result. An interrupt request is generated
if the corresponding SD16IE bit and the GIE bit are set. The SD16 overflow
condition occurs when a conversion result is written to any SD16MEMx
location before the previous conversion result was read.
SD16IV, Interrupt Vector Generator
All SD16 interrupt sources are prioritized and combined to source a single
interrupt vector. SD16IV is used to determine which enabled SD16 interrupt
source requested an interrupt. The highest priority SD16 interrupt request that
is enabled generates a number in the SD16IV register (see register
description). This number can be evaluated or added to the program counter
to automatically enter the appropriate software routine. Disabled SD16
interrupts do not affect the SD16IV value.
Any access, read or write, of the SD16IV register has no effect on the
SD16OVIFG or SD16IFG flags. The SD16IFG flags are reset by reading the
associated SD16MEMx register or by clearing the flags in software.
SD16OVIFG bits can only be reset with software.
If another interrupt is pending after servicing of an interrupt, another interrupt
is generated. For example, if the SD16OVIFG and one or more SD16IFG
interrupts are pending when the interrupt service routine accesses the SD16IV
register, the SD16OVIFG interrupt condition is serviced first and the
corresponding flag(s) must be cleared in software. After the RETI instruction
of the interrupt service routine is executed, the highest priority SD16IFG
pending generates another interrupt request.
Interrupt Delay Operation
The SD16INTDLYx bits control the timing for the first interrupt service request
for the corresponding channel. This feature delays the interrupt request for a
completed conversion by up to four conversion cycles allowing the digital filter
to settle prior to generating an interrupt request. The delay is applied each time
the SD16SC bit is set or when the SD16GAINx or SD16INCHx bits for the
channel are modified. SD16INTDLYx disables overflow interrupt generation
for the channel for the selected number of delay cycles. Interrupt requests for
the delayed conversions are not generated during the delay.