Texas Instruments MSP430x4xx - Manual (Page 431)

SD16_A Operation
22-5 SD16_A
22.2.5 Channel Selection
The SD16_A can convert up to 8 differential pair inputs multiplexed into the
PGA. Up to five input pairs (A0-A4) are available externally on the device. A
resistive divider to measure the supply voltage is available using the A5
multiplexer input. An internal temperature sensor is available using the A6
multiplexer input. Input A7 is a shorted connection between the + and - input
pair and can be used to calibrate the offset of the SD16_A input stage.
Analog Input Setup
The analog input is configured using the SD16INCTL0 and the SD16AE
registers. The SD16INCHx bits select one of eight differential input pairs of the
analog multiplexer. The gain for the PGA is selected by the SD16GAINx bits.
A total of six gain settings are available. The SD16AEx bits enable or disable
the analog input pin. Setting any SD16AEx bit disables the multiplexed digital
circuitry for the associated pin. See the device-specific datasheet for pin
diagrams.
During conversion any modification to the SD16INCHx and SD16GAINx bits
will become effective with the next decimation step of the digital filter. After
these bits are modified, the next three conversions may be invalid due to the
settling time of the digital filter. This can be handled automatically with the
SD16INTDLYx bits. When SD16INTDLY = 00h, conversion interrupt requests
will not begin until the 4
th conversion after a start condition.
The high impedance input buffer can be enabled using the SD16BUFx bits.
The speed settings are selected based on the SD16_A modulator frequency
as shown in Table 22−1.
Table 22−1.High Input Impedance Buffer
SD16BUFx Buffer SD16 Modulator Frequency f
M
00 Buffer disabled
01 Low speed/current f
M
< 200kHz
10 Medium speed/current 200kHz < f
M
< 700kHz
11 High speed/current 700kHz < f
M
< 1.1MHz
22.2.6 Analog Input Characteristics
The SD16 uses a switched-capacitor input stage that appears as an
impedance to external circuitry. The equivalent impedance differs for the PGA
settings and is given in the device-specific datasheet.
An external RC anti-aliasing filter is recommended for the SD16_A to prevent
aliasing of the input signal. The cutoff frequency should be < 10 kHz for a 1 Mhz
modulator clock and OSR = 256. The cutoff frequency may set to a lower
frequency for applications that have lower bandwidth requirements.