Texas Instruments MSP430x4xx - Manual (Page 236)

Timer_B Operation
13-4 Timer_B
13.2 Timer_B Operation
The Timer_B module is configured with user software. The setup and
operation of Timer_B is discussed in the following sections.
13.2.1 16-Bit Timer Counter
The 16-bit timer/counter register, TBR, increments or decrements (depending
on mode of operation) with each rising edge of the clock signal. TBR can be
read or written with software. Additionally, the timer can generate an interrupt
when it overflows.
TBR may be cleared by setting the TBCLR bit. Setting TBCLR also clears the
clock divider and count direction for up/down mode.
Note: Modifying Timer_B Registers
It is recommended to stop the timer before modifying its operation (with
exception of the interrupt enable, interrupt flag, and TBCLR) to avoid errant
operating conditions.
When the TBCLK is asynchronous to the CPU clock, any read from TBR
should occur while the timer is not operating or the results may be
unpredictable. Alternatively, the timer may be read multiple times while
operating, and a majority vote taken in software to determine the correct
reading. Any write to TBR will take effect immediately.
TBR Length
Timer_B is configurable to operate as an 8-, 10-, 12-, or 16-bit timer with the
CNTLx bits. The maximum count value, TBR
(max)
, for the selectable lengths
is 0FFh, 03FFh, 0FFFh, and 0FFFFh, respectively. Data written to the TBR
register in 8-, 10-, and 12-bit mode is right-justified with leading zeros.
Clock Source Select and Divider
The timer clock TBCLK can be sourced from ACLK, SMCLK, or externally via
TBCLK or INCLK. The clock source is selected with the TBSSELx bits. The
selected clock source may be passed directly to the timer or divided by 2,4,
or 8, using the IDx bits. The TBCLK divider is reset when TBCLR is set.