Altera Arria 10 Avalon-ST - Manual (Page 133)

Type 0 Configuration Space Registers
Figure 7-1: Type 0 Configuration Space Registers - Byte Address Offsets and Layout
Endpoints store configuration data in the Type 0 Configuration Space. The Correspondence between
Configuration Space Registers and the PCIe Specification on page 7-1 lists the appropriate section of
the PCI Express Base Specification that describes these registers.
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
Device ID Vendor ID
Status Command
Class Code Revision ID
0x00 Header Type 0x00 Cache Line Size
BAR Registers
BAR Registers
BAR Registers
BAR Registers
BAR Registers
BAR Registers
Reserved
Subsystem Device ID Subsystem Vendor ID
Expansion ROM Base Address
Reserved
Reserved
Capabilities Pointer
0x00 Interrupt Pin Interrupt Line
31 24 23 16 15 8 7 0
PCI Express Capability Structures
Figure 7-2: MSI Capability Structure
0x050
0x054
0x058
Message Control
Configuration MSI Control Status
Register Field Descriptions
Next Cap Ptr
Message Address
Message Upper Address
Reserved Message Data
31 24 23 16 15 8 7 0
0x05C
Capability ID
UG-01145_avst
2015.05.04
Type 0 Configuration Space Registers 7-5
Registers Altera Corporation
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