Altera Arria 10 Avalon-ST - Manual (Page 94)

pld_clk
tx_st_data[127:0]
tx_st_sop
tx_st_eop
tx_st_empty
tx_st_ready
tx_st_valid
tx_st_err
000 CC... CC... CC... CC... CC... CC... CC... CC... CC... CC... CC...
Data Alignment and Timing for the 256‑Bit Avalon‑ST TX Interface
Refer to Figure 8–16 on page 8–15 layout of headers and data for the 256-bit Avalon-ST packets with
qword aligned and qword unaligned addresses.
Single Packet Per Cycle
In single packer per cycle mode, all received TLPs start at the lower 128-bit boundary on a 256-bit
Avalon-ST interface. Turn on Enable Multiple Packets per Cycle on the System Settings tab of the
parameter editor to change multiple packets per cycle.
Single packet per cycle mode requires simpler Application Layer packet decode logic on the TX and RX
paths because packets always start in the lower 128-bits of the Avalon-ST interface. Although this mode
simplifies the Application Layer logic, failure to use the full 256-bit Avalon-ST may slightly reduce the
throughput of a design.
6-28 Data Alignment and Timing for the 256‑Bit Avalon‑ST TX Interface
UG-01145_avst
2015.05.04
Altera Corporation Interfaces and Signal Descriptions
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