Altera Arria 10 Avalon-ST - Manual (Page 269)

Date Version Changes Made
Made the following changes to the user guide:
• Added statement that the bottom left hard IP block includes the
CvP functionality for flip chip packages. For other package types,
the CvP functionality is in the bottom right block.
2014.06.30 14.0
Added the following new features to the Arria 10 Hard IP for PCI
Express:
• Added parameters to enable 256 completion tags with completion
tag checking performed in Application Layer.
• Added simulation log file, altpcie_monitor_sv_dlhip_tlp_file_log.log ,
that is automatically generated in your simulation directory. To
simulation in the Quartus II 14.0 software release, you must
regenerate your IP core to create the supporting monitor file the
generates altpcie_monitor_sv_dlhip_tlp_file_log.log . Refer to
Understanding Simulation Dump File Generation for details.
• Added support for new parameter,User ID register from the
Vendor Sepcific Extended Capability, for Endpoints.
• Added parameter to create a reset pulse at power-up when the soft
reset controller is enabled.
• Simulation support for Phase 2 and Phase 3 equalization when
requested by third-party BFM.
• Increased size of
lmi_addr
to 15 bits.
• Changed the directory structure for generated files. Refer to Files
Generated for Altera IP Cores Targeting Arria 10 for more
information.
• In the Getting Started with the Arria 10 Hard IP for PCI Express
chapter, changed the recommended device to
10AX115R2F40I2LG (Advanced).
Made the following changes to the user guide:
• Added Next Steps in Creating a Design for PCI Express to
Datasheet chapter.
• Corrected frequency range for
hip_reconfig_clk
. It should be
100-125 MHz.
• Corrected Maximum payload size values listed in Reconfigurable
Read-Only Registers table. The maximum size is 2048 bytes.
• Enhanced definition of Device ID and Sub-system Vendor ID to
say that these registers are only valid in the Type 0 (Endpoint)
Configuration Space.
• Changed the default reset controller settings. By default Gen1
devices use the Hard Reset Controller. Gen2 and Gen3 devices use
the Soft Reset Controller.
• Corrected frequencies of
pclk
in Reset and Clocks chapter.
UG-01145_avst
2015.05.04
Revision History for the Avalon-ST Interface C-3
Additional Information Altera Corporation
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