Altera Arria 10 Avalon-ST - Manual (Page 30)

File Name Description
<my_ip>.regmap If the IP contains register information, the .regmap file generates.
The .regmap file describes the register map information of master
and slave interfaces. This file complements the .sopcinfo file by
providing more detailed register information about the system. This
enables register display views and user customizable statistics in
System Console.
<my_ip>.svd Allows HPS System Debug tools to view the register maps of
peripherals connected to HPS within a Qsys system.
During synthesis, the .svd files for slave interfaces visible to System
Console masters are stored in the .sof file in the debug section.
System Console reads this section, which Qsys can query for register
map information. For system slaves, Qsys can access the registers by
name.
<my_ip>.v
or
<my_ip>.vhd
HDL files that instantiate each submodule or child IP core for
synthesis or simulation.
mentor/ Contains a ModelSim ® script
msim_setup.tcl
to set up and run a
simulation.
aldec/ Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a
simulation.
/synopsys/vcs
/synopsys/vcsmx
Contains a shell script vcs_setup.sh to set up and run a VCS ®
simulation.
Contains a shell script
vcsmx_setup.sh and synopsys_ sim.setup file to
set up and run a VCS MX ® simulation.
/cadence Contains a shell script
ncsim_setup.sh
and other setup files to set up
and run an NCSIM simulation.
/submodules Contains HDL files for the IP core submodule.
<child IP cores>/
For each generated child IP core directory, Qsys generates
/synth
and
/
sim sub-directories.
UG-01145_avst
2015.05.04
Files Generated for Altera IP Cores 2-11
Getting Started with the Arria 10 Hard IP for PCI Express Altera Corporation
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