Altera Arria 10 Avalon-ST User Manual
Page 42
# INFO: 48089 ns RP LTSSM State: L0
# INFO: 48133 ns EP LTSSM State: L0
# INFO: 48226 ns Configuring Bus 000, Device 000, Function 00
# INFO: 48226 ns RP Read Only Configuration Registers:
# INFO: 48226 ns Vendor ID: 1556
# INFO: 48226 ns Device ID: 5555
# INFO: 48226 ns Revision ID: 00
# INFO: 48226 ns Class Code: 040000
# INFO: 48706 ns ECRC Check Capable: Supported
# INFO: 48706 ns ECRC Generation Capable: Supported
# INFO: 48738 ns RP PCI Express Slot Capability
# INFO: 48738 ns Power Controller: Not Present
# INFO: 48738 ns MRL Sensor: Not Present
# INFO: 48738 ns Attention Indicator: Not Present
# INFO: 48738 ns Power Indicator: Not Present
# INFO: 48738 ns Hot-Plug Surprise: Not Supported
# INFO: 48738 ns Hot-Plug Capable: Not Supported
# INFO: 48738 ns Slot Power Limit Value: 0
# INFO: 48738 ns Slot Power Limit Scale: 0
# INFO: 48738 ns Physical Slot Number: 0
# INFO: 48738 ns Activity_toggle flag is set
# INFO: 48802 ns RP PCI Express Link Status Register (0081):
# INFO: 48802 ns RP PCI Express Max Link Speed (0002):
# INFO: 48802 ns RP PCI Express Current Link Speed (0001):
# INFO: 48802 ns Negotiated Link Width: x8
# INFO: 48802 ns Slot Clock Config: Local Clock Used
# INFO: 48834 ns Current Link Speed: 2.5GT/s
# INFO: 48889 ns RP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 49669 ns EP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 50501 ns EP LTSSM State: RECOVERY.RCVRCFG
# INFO: 51209 ns RP LTSSM State: RECOVERY.RCVRCFG
# INFO: 48889 ns RP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 53669 ns EP LTSSM State: RECOVERY.SPEED
# INFO: 54721 ns RP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 54746 ns Wait for Link to enter L0 after negotiated to
# the expected speed of EP Target Link Speed 0002):
# INFO: 53337 ns RP LTSSM State: RECOVERY.SPEED
# INFO: 55235 ns EP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 56299 ns EP LTSSM State: RECOVERY.RCVRCFG
# INFO: 57163 ns RP LTSSM State: RECOVERY.RCVRCFG
# INFO: 57707 ns RP LTSSM State: RECOVERY.IDLE
# INFO: 57979 ns EP LTSSM State: RECOVERY.IDLE
# INFO: 58035 ns RP LTSSM State: L0
# INFO: 58075 ns EP LTSSM State: L0
# INFO: 58090 ns New Link Speed: 5.0GT/s
# INFO: 58106 ns RP PCI Express Link Control Register (0000):
# INFO: 58106 ns Common Clock Config: Local Clock
# INFO: 70602 ns Completed configuration of Endpoint BARs.
# INFO: 70602 ns TASK:my_test Setup
# INFO: 70602 ns TASK:my_test Write to 32bit register at
# addr = 0x0 with wdata=0xBABEFACE
# INFO: 70610 ns TASK:my_test Read from 32bit register at
# addr 0x00000000
# INFO: 71298 ns TASK:my_test Register compare matches!
# INFO: 71298 ns TASK:my_test Write to 32bit register at
# 0x00000004 Actual 0x12345678
# INFO: 71306 ns TASK:my_test => 1.22 Read from 32bit register
# at addr = 0x00000004
# INFO: 71994 ns TASK:my_test => 1.23 Register compare matches!
# INFO 71994 ns TASK:my_test => 2.11 Fill write memory with
# QWORD_INC pattern
# INFO: 71994 ns TASK:my_test Memory write burst at addr=0x00
# with wdata=0x10203040
# INFO: 72002 ns TASK:my_test => 2.21 Memory Read burst
# INFO: 72690 ns TASK:my_test Memory write burst at addr=0x04
# with wdata=0x10203040
# INFO: 72698 ns TASK:my_test Memory Read burst
3-12
Partial Transcript for Configuration Space Bypass Simulation
UG-01145_avst
2014.08.18
Altera Corporation
Getting Started with the Configuration Space Bypass Mode Qsys Example Design