Altera Arria 10 Avalon-ST - Manual (Page 184)

Message Root Port Endpoint
Generated by
Comments App
Layer
Core Core (with
App Layer
input)
Attentio
n
Button_
Pressed
(Endpoi
nt only)
Receive Transmit No No Yes
N/A
Related Information
PCI Express Base Specification Revision 3.0
Transaction Layer Routing Rules
Transactions adhere to the following routing rules:
• In the receive direction (from the PCI Express link), memory and I/O requests that match the defined
base address register (BAR) contents and vendor-defined messages with or without data route to the
receive interface. The Application Layer logic processes the requests and generates the read
completions, if needed.
• In Endpoint mode, received Type 0 Configuration requests from the PCI Express upstream port route
to the internal Configuration Space and the Arria 10 Hard IP for PCI Express generates and transmits
the completion.
• The Hard IP handles supported received message transactions (Power Management and Slot Power
Limit) internally. The Endpoint also supports the Unlock and Type 1 Messages. The Root Port
supports Interrupt, Type 1, and error Messages.
• Vendor-defined Type 0 Message TLPs are passed to the Application Layer.
• The Transaction Layer treats all other received transactions (including memory or I/O requests that do
not match a defined BAR) as Unsupported Requests. The Transaction Layer sets the appropriate error
bits and transmits a completion, if needed. These Unsupported Requests are not made visible to the
Application Layer; the header and data are dropped.
• For memory read and write request with addresses below 4 GB, requestors must use the 32-bit format.
The Transaction Layer interprets requests using the 64-bit format for addresses below 4 GB as an
Unsupported Request and does not send them to the Application Layer. If Error Messaging is enabled,
an error Message TLP is sent to the Root Port. Refer to Transaction Layer Errors for a comprehensive
list of TLPs the Hard IP does not forward to the Application Layer.
• The Transaction Layer sends all memory and I/O requests, as well as completions generated by the
Application Layer and passed to the transmit interface, to the PCI Express link.
• The Hard IP can generate and transmit power management, interrupt, and error signaling messages
automatically under the control of dedicated signals. Additionally, it can generate MSI requests under
the control of the dedicated signals.
• In Root Port mode, the Application Layer can issue Type 0 or Type 1 Configuration TLPs on the
Avalon-ST TX bus.
12-6 Transaction Layer Routing Rules
UG-01145_avst
2015.05.04
Altera Corporation Transaction Layer Protocol (TLP) Details
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