Root port testbench, Root port testbench -3 – Altera Arria 10 Avalon-ST User Manual
Page 203
The top-level of the testbench instantiates four main modules:
• <qsys_systemname>— This is the example Endpoint design. For more information about this module,
refer to Chaining DMA Design Examples.
• altpcietb_bfm_top_rp.v—This is the Root Port PCI Express BFM. For more information about this
module, refer to Root Port BFM.
• altpcietb_pipe_phy—There are eight instances of this module, one per lane. These modules intercon‐
nect the PIPE MAC layer interfaces of the Root Port and the Endpoint. The module mimics the
behavior of the PIPE PHY layer to both MAC interfaces.
• altpcietb_bfm_driver_chaining—This module drives transactions to the Root Port BFM. This is the
module that you modify to vary the transactions sent to the example Endpoint design or your own
design. For more information about this module, refer to Root Port Design Example.
In addition, the testbench has routines that perform the following tasks:
• Generates the reference clock for the Endpoint at the required frequency.
• Provides a PCI Express reset at start up.
Note: Before running the testbench, you should set the following parameters in
<instantiation_name>_tb/
sim/<instantiation_name>_tb.v
:
•
serial_sim_hwtcl
: Set to 1 for serial simulation and 0 for PIPE simulation.
•
enable_pipe32_sim_hwtcl
: Set to 0 for serial simulation and 1 for PIPE simulation.
Related Information
•
Getting Started with the Arria 10 Hard IP for PCI Express
•
on page 17-4
•
•
on page 17-20
Root Port Testbench
This testbench simulates up to an ×8 PCI Express link using either the PIPE interfaces of the Root Port
and Endpoints or the serial PCI Express interface. The testbench design does not allow more than one
PCI Express link to be simulated at a time. The top-level of the testbench instantiates four main modules:
• <qsys_systemname>— Name of Root Port This is the example Root Port design. For more information
about this module, refer to Root Port Design Example.
• altpcietb_bfm_ep_example_chaining_pipen1b—This is the Endpoint PCI Express mode described in
the section Chaining DMA Design Examples.
• altpcietb_pipe_phy—There are eight instances of this module, one per lane. These modules connect
the PIPE MAC layer interfaces of the Root Port and the Endpoint. The module mimics the behavior of
the PIPE PHY layer to both MAC interfaces.
• altpcietb_bfm_driver_rp—This module drives transactions to the Root Port BFM. This is the module
that you modify to vary the transactions sent to the example Endpoint design or your own design. For
more information about this module, see Test Driver Module.
UG-01145_avst
2015.05.04
Root Port Testbench
17-3
Testbench and Design Example
Altera Corporation