Altera Arria 10 Avalon-ST - Manual (Page 206)

The block diagram contains the following elements:
• Endpoint DMA write and read requester modules.
• The chaining DMA design example connects to the Avalon-ST interface of the Arria 10 Hard IP for
PCI Express. The connections consist of the following interfaces:
• The Avalon-ST RX receives TLP header and data information from the Hard IP block
• The Avalon-ST TX transmits TLP header and data information to the Hard IP block
• The Avalon-ST MSI port requests MSI interrupts from the Hard IP block
• The sideband signal bus carries static information such as configuration information
• The descriptor tables of the DMA read and the DMA write are located in the BFM shared memory.
• A RC CPU and associated PCI Express PHY link to the Endpoint design example, using a Root Port
and a north/south bridge.
The example Endpoint design Application Layer accomplishes the following objectives:
• Shows you how to interface to the Arria 10 Hard IP for PCI Express using the Avalon-ST protocol.
• Provides a chaining DMA channel that initiates memory read and write transactions on the PCI
Express link.
• If the ECRC forwarding functionality is enabled, provides a CRC Compiler IP core to check the ECRC
dword from the Avalon-ST RX path and to generate the ECRC for the Avalon-ST TX path.
The following modules are included in the design example and located in the subdirectory
<qsys_systemname>/testbench/<qsys_system_name>_tb/simulation/submodules :
• <qsys_systemname> —This module is the top level of the example Endpoint design that you use for
simulation.
This module provides both PIPE and serial interfaces for the simulation environment. This module
has a
test_in
debug ports. Refer to Test Signalswhich allow you to monitor and control internal states
of the Hard IP.
For synthesis, the top level module is
<qsys_systemname>/synthesis/submodules . This module instantiates
the top-level module and propagates only a small sub-set of the test ports to the external I/Os. These
test ports can be used in your design.
• <variation name>.v or <variation name>.vhd— Because Altera provides five sample parameteriza‐
tions, you may have to edit one of the provided examples to create a simulation that matches your
requirements. <variation name>.v or <variation name>.vhd— Because Altera provides five sample
parameterizations, you may have to edit one of the provided examples to create a simulation that
matches your requirements.
The chaining DMA design example hierarchy consists of these components:
• A DMA read and a DMA write module
• An on-chip Endpoint memory (Avalon-MM slave) which uses two Avalon-MM interfaces for each
engine
The RC slave module is used primarily for downstream transactions which target the Endpoint on-chip
buffer memory. These target memory transactions bypass the DMA engines. In addition, the RC slave
17-6 Chaining DMA Design Examples
UG-01145_avst
2015.05.04
Altera Corporation Testbench and Design Example
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