Altera Arria 10 Avalon-ST User Manual

Page 47

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Parameter

Value

Description

Enable byte

parity ports on

Avalon-ST

interface

On/Off

When On, the RX and TX datapaths are parity protected. Parity is

odd.
This parameter is only available for the Avalon-ST Arria 10 Hard

IP for PCI Express.

Enable

multiple

packets per

cycle

On/Off

When On, the 256-bit Avalon-ST interface supports the transmis‐

sion of TLPs starting at any 128-bit address boundary, allowing

support for multiple packets in a single cycle. To support multiple

packets per cycle, the Avalon-ST interface includes 2 start of packet

and end of packet signals for the 256-bit Avalon-ST interfaces. This

feature is only supported for Gen3 ×8.
For more information refer to

Tradeoffs to Consider when

Enabling Multiple Packets per Cycle

on page 6-15 and

Multiple

Packets per Cycle on the Avalon-ST TX 256-Bit Interface

on page

6-30.

Enable

configuration

via Protocol

(CvP)

On/Off

When On, the Quartus II software places the Endpoint in the

location required for configuration via protocol (CvP). For more

information about CvP, click the Configuration via Protocol (CvP)

link below.

Enable credit

consumed

selection port

On/Off

When you turn on this option, the core includes the

tx_cons_

cred_sel

port. This parameter does not apply to the Avalon-MM

interface.

Enable

Configuration

bypass

(CfgBP)

On/Off

When On, the Arria 10 Hard IP for PCI Express bypasses the

Transaction Layer Configuration Space registers included as part of

the Hard IP, allowing you to substitute a custom Configuration

Space implemented in soft logic.
This parameter is not available for the Avalon-MM IP Cores.

Enable

dynamic

reconfigura‐

tion of PCIe

read-only

registers

On/Off

When On, you can use the Hard IP reconfiguration bus to

dynamically reconfigure Hard IP read-only registers. For more

information refer to Hard IP Reconfiguration Interface.

Enable local

management

interface

(LMI)

On/Off

When On, your variant includes the optional LMI interface. This

interface is used to log error descriptor information in the TLP

header log registers. The LMI interface provides the same access to

Configuration Space registers as Configuration TLP requests.

4-4

System Settings

UG-01145_avst

2014.08.18

Altera Corporation

Parameter Settings

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