Altera Arria 10 Avalon-ST - Manual (Page 267)

Additional Information
C
2015.05.04
UG-01145_avst Subscribe
Send Feedback
Revision History for the Avalon-ST Interface
Date Version Changes Made
2015.05.04 15.0 Made the following changes to the Arria 10 user guide:
• Added to description of Data Link Layer link active bit. It is only
available for Root Ports. It is always 0 for Endpoints.
• Corrected link to Arria 10 Avalon-MM DMA Interface for PCIe
Solutions User Guide.
• Added Enable Altera Debug Master Endpoint (ADME)
parameter to support optional Native PHY register programming
with the Altera System Console.
• Added information about the custom example designs, in Arria
10 Avalon-ST Example Designs on page 1-9. This feature is
available for this IP core starting in the IP core release 14.1.
• Removed list of static example designs from Arria 10 Avalon-ST
Example Designs on page 1-9. You can derive the list from the
installation directory where example designs are available.
• Enhanced descriptions of channel placement, added fPLL
placement for Gen1 and Gen2 data rates, and added master CGB
location, in Physical Layout of Hard IP In Arria 10 Devices on
page 5-1.
• Added column for Avalon-ST Interface with SR-IOV variations in
Feature Comparison for all Hard IP for PCI Express IP Cores table
in Arria 10 Features section. Moved supported TLPs information
to separate table. Updated information in tables.
• Removed Migration and TLP Format appendices, and added new
appendix Frequently Asked Questions on page 19-1.
• Corrected LMI Write figure in LMI Signals on page 6-42.
• Corrected MSI-X Interrupt Components figure in Implementing
MSI-X Interrupts on page 9-4.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134