Altera Arria 10 Avalon-ST - Manual (Page 16)

PCIe Link
PCIe Hard IP
RP
Switch
PCIe
Hard IP
RP
User Application
Logic
PCIe Hard IP
EP
PCIe Link PCIe Link
User Application
Logic
Altera FPGA Hard IP for PCI Express
Altera FPGA with Hard IP for PCI Express
Active Serial or
Active Quad
Device Configuration
Configuration via Protocol (CvP)
using the PCI Express Link
Serial or
Quad Flash
USB
Download
cable
PCIe
Hard IP
EP
User
Application
Logic
Altera FPGA with Hard IP for PCI Express
Config
Control
CVP
USB
Host CPU
PCIe
Related Information
Configuration via Protocol (CvP)Implementation in Altera FPGAs User Guide
Arria 10 Avalon-ST Example Designs
Altera provides example designs to familiarize you with the available functionality. Each design connects
the device under test (DUT) to an application programming platform (APP), labeled APPs in the figure
below. Starting in the Quartus II 14.1 release, if you change these parameters Qsys updates the testbench
to match the parameters you've selected.
UG-01145_avst
2015.05.04
Arria 10 Avalon-ST Example Designs 1-9
Datasheet Altera Corporation
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