Altera Arria 10 Avalon-ST - Manual (Page 28)

Files Generated for Altera IP Cores
The Quartus II software generates the following IP core output file structure:
Figure 2-5: IP Core Generated Files
<your_testbench>_tb.csv
<your_testbench>_tb.spd
<your_ip>.cmp - VHDL component declaration file
<your_ip>.ppf - XML I/O pin information file
<your_ip>.qip - Lists IP synthesis files
<your_ip>.sip - Contains assingments for IP simulation files
<your_ip>.v or .vhd
Top-level IP synthesis file <your_ip>.v or .vhd
Top-level simulation file
<simulator_setup_scripts>
<your_ip>.qsys - System or IP integration file
<your_ip>_bb.v - Verilog HDL black box EDA synthesis file
<your_ip>_inst.v or .vhd - Sample instantiation template
<your_ip>_generation.rpt - IP generation report
<your_ip>.debuginfo - Contains post-generation information
<your_ip>.html - Connection and memory map data
<your_ip>.bsf - Block symbol schematic
<your_ip>.spd - Combines simulation scripts for multiple cores
<your_ip>_tb.qsys
Testbench system file
<your_ip>.sopcinfo - Software tool-chain integration file
<project directory>
<EDA tool setup
scripts>
<your_ip>
IP variation files
<testbench>_tb
testbench system
sim
Simulation files
synth
IP synthesis files
sim
simulation files
<EDA tool name>
Simulator scripts
<testbench>_tb
<ip subcores> n
Subcore libraries
sim
Subcore
Simulation files
synth
Subcore
synthesis files
<HDL files> <HDL files>
<your_ip> n
IP variation files
testbench files
Table 2-4: IP Core Generated Files
File Name Description
<my_ip>.qsys The Qsys system or top-level IP variation file. <my_ip> is the name
that you give your IP variation.
UG-01145_avst
2015.05.04
Files Generated for Altera IP Cores 2-9
Getting Started with the Arria 10 Hard IP for PCI Express Altera Corporation
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