Design -1 – Altera Arria 10 Avalon-ST User Manual
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Getting Started with the Configuration Space
Bypass Mode Qsys Example Design
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This Qsys design example demonstrates Configuration Space Bypass mode for the Arria 10 Hard IP for
PCI Express IP Core. A Root Port BFM provides stimulus to the Endpoint design. The Endpoint bypasses
the standard Configuration Space to access the custom Configuration Space and memory of two
functions. The Configuration Space Bypass Example Design performs the following functions:
• Accepts Configuration, Memory, and Message TLPs on the Arria 10 Hard IP for PCI Express RX
Avalon-ST interface
• Translates Type 0 Configuration Read and Configuration Write Requests to Avalon-MM read and
write requests that target the Configuration Space of either Function 0 or Function 1.
• Responds to invalid Type 0 Configuration Requests with an Unsupported Request (UR) status in a
Completion Message.
• Converts single dword Memory Read and Memory Write Requests to access 32-bit registers of the
target function using the Avalon-MM interface.
• Maps two contiguous MBytes of memory for the two functions with the first MByte for Function 0 and
the second MByte for Function 1.
• Sets up two registers for each function.
• Drops the following invalid Write Requests:
• Memory Write Requests with a payload of more than one dword
• Messages with data
• Returns Completer Abort (CA) status in Completion message for invalid Memory Read Requests such
as Memory Read Requests with a payload greater than one dword.
• Returns a Completion Status of Successful Completion for valid Configuration Requests to Function 0
and Function 1.
The following figure illustrates, the components of the Configuration Space Bypass Mode Qsys Example
Design. The example design includes the following components:
• DUT: The Arria 10 Hard IP for PCI Express. The example turns on the Enable Configuration Space
Bypass parameter.
• APPS: The Configuration Space Bypass application demonstrates Configuration Space Bypass mode.
• pcie_reconfig_driver_0: The PCIe Reconfig Driver drives the Transceiver Reconfiguration Controller.
This driver is a plain text Verilog HDL file that you can modify if necessary to meet your system
requirements.
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