Hard IP Reconfiguration Interface .........................................................................................................6-52
Power Management Signals .................................................................................................................... 6-54
Physical Layer Interface Signals ..............................................................................................................6-57
Serial Data Signals .........................................................................................................................6-57
PIPE Interface Signals .................................................................................................................. 6-57
Test Signals .................................................................................................................................... 6-62
Registers...............................................................................................................7-1
Correspondence between Configuration Space Registers and the PCIe Specification ..................... 7-1
Type 0 Configuration Space Registers ..................................................................................................... 7-5
PCI Express Capability Structures.............................................................................................................7-5
Altera-Defined VSEC Registers................................................................................................................. 7-8
CvP Registers................................................................................................................................................ 7-9
Uncorrectable Internal Error Mask Register ........................................................................................ 7-12
Uncorrectable Internal Error Status Register ....................................................................................... 7-13
Correctable Internal Error Mask Register .............................................................................................7-14
Correctable Internal Error Status Register ............................................................................................7-14
Arria 10 Reset and Clocks................................................................................... 8-1
Reset Sequence for Hard IP for PCI Express IP Core and Application Layer ....................................8-2
Clocks ........................................................................................................................................................... 8-4
Clock Domains ................................................................................................................................8-4
Clock Summary ...............................................................................................................................8-6
Interrupts.............................................................................................................9-1
Interrupts for Endpoints.............................................................................................................................9-1
MSI Interrupts .................................................................................................................................9-1
MSI-X ............................................................................................................................................... 9-4
Implementing MSI-X Interrupts................................................................................................... 9-4
Legacy Interrupts ............................................................................................................................ 9-6
Interrupts for Root Ports ........................................................................................................................... 9-7
Error Handling ................................................................................................. 10-1
Physical Layer Errors ................................................................................................................................10-2
Data Link Layer Errors .............................................................................................................................10-2
Transaction Layer Errors .........................................................................................................................10-3
Error Reporting and Data Poisoning ..................................................................................................... 10-6
Uncorrectable and Correctable Error Status Bits .................................................................................10-7
IP Core Architecture......................................................................................... 11-1
Top-Level Interfaces .................................................................................................................................11-3
Avalon-ST Interface ......................................................................................................................11-3
Clocks and Reset ........................................................................................................................... 11-4
Local Management Interface (LMI Interface) .......................................................................... 11-4
Hard IP Reconfiguration ............................................................................................................. 11-4
TOC-4
Getting Started with the Arria 10 Hard IP for PCI Express with the Avalon-ST Interface
Altera Corporation
