Altera Arria 10 Avalon-ST - Manual (Page 74)

Packet TLP
Data<n> pcie_data_byte<4n+3>, pcie_data_byte<4n+2>, pcie_data_byte<4n+1>, pcie_data_
byte<n>
The following figure illustrates the mapping of Avalon-ST RX packets to PCI Express TLPs for a three
dword header with non-qword aligned addresses with a 64-bit bus. In this example, the byte address is
unaligned and ends with 0x4, causing the first data to correspond to
rx_st_data[63:32]
.
Note: The Avalon-ST protocol, as defined in Avalon Interface Specifications, is big endian, while the Hard
IP for PCI Express packs symbols into words in little endian format. Consequently, you cannot use
the standard data format adapters available in Qsys.
Figure 6-3: 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with Non-Qword
Aligned Address
pld_clk
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
Header1 Data0 Data2
Header0 Header2 Data1
The following figure illustrates the mapping of Avalon-ST RX packets to PCI Express TLPs for a three
dword header with qword aligned addresses. Note that the byte enables indicate the first byte of data is
not valid and the last dword of data has a single valid byte.
Figure 6-4: 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with Qword
Aligned Address
clk
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
Header 1 Data1 Data3
Header 0 Header2 Data0 Data2
6-8 Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface
UG-01145_avst
2015.05.04
Altera Corporation Interfaces and Signal Descriptions
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