Using relaxed ordering, Using relaxed ordering -9 – Altera Arria 10 Avalon-ST User Manual
Page 187
Can the Row Pass
the Column?
Posted Req
Non Posted Req
Completion
Memory Write or
Message Req
Read Request
I/O or Cfg Write Req
Cm
pl
Cmpl
No
Y/N
No
No
Yes
Yes
Yes
Yes
Y/N
No
No
No
I/O or
Configu‐
ration
Write
Cmpl
Y/N
No
Yes
Yes
Yes
Yes
Y/N
No
As the table above indicates, the RX datapath implements an RX buffer reordering function that allows
Posted and Completion transactions to pass Non-Posted transactions (as allowed by PCI Express ordering
rules) when the Application Layer is unable to accept additional Non-Posted transactions.
The Application Layer dynamically enables the RX buffer reordering by asserting the
rx_mask
signal. The
rx_mask
signal blocks non-posted Req transactions made to the Application Layer interface so that only
posted and completion transactions are presented to the Application Layer.
Note: MSI requests are conveyed in exactly the same manner as PCI Express memory write requests and
are indistinguishable from them in terms of flow control, ordering, and data integrity.
Related Information
Using Relaxed Ordering
Transactions from unrelated threads are unlikely to have data dependencies. Consequently, you may be
able to use relaxed ordering to improve system performance. The drawback is that only some transactions
can be optimized for performance. Complete the following steps to decide whether to enable relaxed
ordering in your design:
1. Create a system diagram showing all PCI Express and legacy devices.
2. Analyze the relationships between the components in your design to identify the following hazards:
a. Race conditions: A race condition exists if a read to a location can occur before a previous write to
that location completes. The following figure shows a data producer and data consumer on
opposite sides of a PCI-to-PCI bridge. The producer writes data to the memory through a PCI-to-
PCI bridge. The consumer must read a flag to confirm the producer has written the new data into
the memory before reading the data. However, because the PCI-to-PCI bridge includes a write
buffer, the flag may indicate that it is safe to read data while the actual data remains in the PCI-to-
PCI bridge posted write buffer.
UG-01145_avst
2015.05.04
Using Relaxed Ordering
12-9
Transaction Layer Protocol (TLP) Details
Altera Corporation