Altera Arria 10 Avalon-ST User Manual
Page 171
The Configuration Space also generates all messages (PME#, INT, error, slot power limit), MSI requests,
and completion packets from configuration requests that flow in the direction of the root complex, except
slot power limit messages, which are generated by a downstream port. All such transactions are
dependent upon the content of the PCI Express Configuration Space as described in the PCI Express Base
Specification.
Related Information
•
Type 0 Configuration Space Registers
•
Type 1 Configuration Space Registers
•
Error Checking and Handling in Configuration Space Bypass Mode
In Configuration Space Bypass mode, the Application Layer receives all TLPs that are not malformed. The
Transaction Layer detects and drops malformed TLPs. Refer to “Errors Detected by the Transaction
Layer” on page 15–3 for the malformed TLPs the Transaction Layer detects. The Transaction Layer also
detects Internal Errors and Corrected Errors. Real-time error status signals report Internal Errors and
Correctable Errors to the Application Layer. The Transaction Layer also records these errors in the AER
registers. You can access the AER registers using the LMI interface.
Because the AER header log is not available in Configuration Space Bypass Mode, the Application Layer
must implement logic to read the AER header log using the LMI interface. You may need to arbitrate
between Configuration Space Requests to the AER registers of the Hard IP for PCI Express and Configu‐
ration Space Requests to your own Configuration Space. Or, you can avoid arbitration logic by deasserting
the
ready
signal until each LMI access completes.
Note: Altera does not support the use of the LMI interface to read and write the other registers in
function0 of the Hard IP for PCI Express Configuration Space. You must create your own
function0 in your application logic.
In Configuration Space Bypass mode, the Transaction Layer disables checks for Unsupported Requests
and Unexpected Completions. The Application Layer must implement these checks. The Transaction
Layer also disables error Messages and completion generation, which the Application Layer must
implement.
Note: The following figure shows the division of error checking between the Transaction Layer of the
hard IP for PCI Express and the Application Layer. The real-time error flags assert for one
pld_clk
as the errors are detected by the Transaction Layer.
UG-01145_avst
2014.08.18
Error Checking and Handling in Configuration Space Bypass Mode
11-7
IP Core Architecture
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