FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 110)

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CHAPTER 4 I/O PORTS
4.6.2 Operation of Port 4
This section describes the operations of the port 4.
■ Operation of port 4
●
Operation as an output port
• Setting the corresponding DDR4 register bit to "1" sets a pin as an output port.
• When a pin is as an output port, the output transistor is enabled and the pin outputs the data stored in the
output latch.
• Writing data to the PDR4 register stores the data in the output latch and outputs the data to the pin.
• Reading the PDR4 register returns the pin value.
●
Operation as an input port
• Setting the corresponding DDR4 register bit to "0" sets a pin as an input port.
• When a pin is set as an input port, the output transistor is "OFF" and the pin goes to the high-impedance
state.
• Writing data to the PDP4 register stores the data in the output latch but does not output the data to the
pin.
• Reading the PDR4 register returns the pin value.
●
Operation as a peripheral output
• If a peripheral output enable bit is set to "enable", the corresponding pin becomes a peripheral output.
• As the pin value can be read even if the peripheral output is enabled, the peripheral output value can be
read via the PDR4 register.
●
Operation as a peripheral input
• A port pin is set as a peripheral input by setting the corresponding DDR4 register bit to "0".
• Reading the PDR4 register returns the pin value, regardless of whether or not the peripheral is using the
input pin.
●
Operation at reset
• Resetting the CPU initializes the DDR4 register value to "0". This sets output transistors "OFF" (pins
become input ports) and sets the pins to the high-impedance state.
• The PDR4 register is not initialized by a reset. Therefore, to use as output port, the output data must be
set in the PDR4 register before setting the corresponding DDR4 register bit to output mode.