FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 60)

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CHAPTER 3 CPU
3.5.2 Reset Operation
When the CPU wakes up from a reset, the CPU selects the read address of the mode
data and reset vector according to the mode pin settings, then performs a mode fetch.
The mode fetch is performed after the oscillation stabilization delay time has passed
when power is turned on to a product with power-on reset, or on wake-up from stop
mode by a reset. If reset occurs during a write to RAM, the contents of the RAM address
cannot be assured.
■ Overview of reset operation
Figure 3.5-2 Reset operation flow diagram
During reset
Mode fetch
(reset operation)
Normal operation
(RUN state)
Software reset
Watchdog reset
NO
NO
NO
External reset input
Power-on reset
selected?
YES
YES
YES
Power-on
Wakes up from external
Fetch mode data
Fetch reset vector
Fetch the instruction code from the address
indicated by the reset vector and begin execution.
Power-on reset
(optional)
Main clock oscillation
stabilization delay reset
operation
reset?
or stop mode?
state
Main clock oscillation
stabilization delay reset
state