FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 172)

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CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC)
Figure 8.5-4 Operation in one-shot timer mode
Note:
Do not modify PCR2 when the counter is operating (PCR1: EN = "1").
References:
• The UF bit is set to "1" if counter underflows (01
H
--> 00
H
), regardless of the value of the interrupt
request enable bit (PCR1: IE).
• When the counter is stopped (PCR1: EN = "0") while the interval timer function is selected, the TO bit
maintains the value it had immediately before the counter stopped.
Counter value FF H
80 H
00 H
Timer cycle
Cleared by the program
Time
UF bit
EN bit
TOE bit
RLBR value
(FF
H )
(TO bit)
Automatic clear Reactivate
Invert
Reactivates with the initial value unchanged ("0")
For an initial value of "1" on activation
*: If the PWC reload buffer register (RLBR) value is modified during operation, the new value will be effective in next cycle.
Automatic clear Automatic clear Reactivate
RLBR value is modified (FF H 80 H ) *