FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 123)

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CHAPTER 5 TIMEBASE TIMER
5.6 Notes on Using Timebase Timer
This section lists points to note when using the timebase timer.
■ Notes on using timebase timer
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Notes on setting bits by program
The system cannot recover from interrupt processing if the overflow interrupt request flag bit (TBTC:
TBIF) is "1" and the interrupt request enable bit is enabled (TBTC: TBIE = "1"). Always clear the TBIF
bit.
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Clearing timebase timer
In addition to being cleared by the timebase timer initialization bit (TBTC: TBR = "0"), the timer is cleared
whenever the main clock oscillation stabilization delay time is required. When the timebase timer is
selected as a count clock of the watchdog timer, clearing the timebase timer also clears the watchdog timer.
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Using as timer for oscillation stabilization delay time
As the main clock oscillation frequency is stopped when the power is turned on during stop mode, the
timebase timer provides the oscillation stabilization delay time after the oscillator starts.
An appropriate oscillation stabilization delay time must be selected for the type of resonator connected to
the main clock oscillator (clock generator).
See Section 3.6.1 "Clock Generator".
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Notes on peripheral functions that provided a clock supply from timebase timer
In modes in which the main clock oscillation frequency is stopped, the timebase timer also stops, and the
counter is cleared.
As the clock derived from the timebase timer restarts output from its initial state when the timebase timer
counter is cleared, the "H" level may be shorter or the "L" level longer by a maximum of half cycle. The
clock of the watchdog timer also restarts output from its initial state.