FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 53)

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CHAPTER 3 CPU
3.4.3 Multiple Interrupts
Multiple interrupts can be performed by setting different interrupt levels to the interrupt
level setting register for two or more interrupt requests from peripheral functions.
■ Multiple interrupts
If the interrupt request having the higher interrupt levels occurs during the interrupt processing routines, the
CPU halts the current interrupt process and switches to accept the interrupt with the higher priority.
Interrupt levels can be set in the range 1 to 3. However, the CPU does not accept interrupt requests set to
interrupt level 3.
●
Example of multiple interrupts
As an example of multiple interrupt processing, assume that an external interrupt has a higher priority than
the timer interrupt. The timer interrupt is set to level 2 and the external interrupt is set to level 1. Figure 3.4-
3 "Example of multiple interrupts" shows the processing when the external interrupt occurs during
execution of timer interrupt processing.
Figure 3.4-3 Example of multiple interrupts
• During execution of timer interrupt processing, the interrupt level bits in the condition code register
(CCR:IL1, IL0) are automatically set to the same value as the interrupt level setting register (ILR1,
ILR2, ILR3) corresponding to the timer interrupt (level 2 in this example). If the interrupt request set to
higher interrupt level (level 1 in this example) occurs at this time, the interrupt processing has priority.
• To temporarily disable multiple interrupts during the timer interrupt, the interrupt enable flag in the
condition code register is set to "interrupts disabled" (CCR: I = "0") or the interrupt level bits (IL1, IL0)
set to "00
B
".
• On execution of the interrupt return instruction (RETI) at the completion of interrupt processing, the
CPU restores the program counter (PC) and program status (PS) values saved on the stack and resumes
execution of the interrupted program.
Restoring the program status (PS) returns the condition code register (CCR) to the value prior to the
interrupt.
(4)
(5) (6)
(7)
(1)
(2)
(3)
(8)
Main program
Initialize peripheral
Timer interrupt occurs
Restart main program
Interrupt level 2
(CCR:IL1, IL0 = "10")
Timer interrupt processing
External interrupt
Halt
Restart
Timer interrupt
Timer interrupt returns
processing
Interrupt level 1
(CCR:IL1, IL0 = "01")
External interrupt processing
External interrupt
processing
External interrupt
returns
occurs