FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 220)

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CHAPTER 10 UART
Table 10.4-1 Serial mode control register 1 (SMC1) bits
Bit Function
Bit 7 PEN:
Parity control bit • In the clock asynchronous mode, sets whether there is parity data or not.
Bit 6 SBL:
Stop bit length
control bit • This bit determines the stop bit length.
• In serial transmission, a stop bit of the bit length specified is appended.
• In serial reception, a stop bit is recognized as in a 1-bit length regardless of the value
set here.
Bit 5
Bit 4 MC1, MC0:
Transfer mode
control bits • These two bits determine the transfer mode (data length).
Bit 3 SMDE:
Operation mode
control bit • This bit selects the UART operating mode. In asynchronous mode, the UART
operates on the serial clock divided by 8. In clock synchronous mode, it operates on
the selected serial clock.
Bit 2 Unused bit • The read value is indeterminate.
• Writing to this bit has no effect on the operation.
Bit 1 SCKE:
Serial clock output
bit • This bit selects either serial clock input/output (SCK) of the serial clock synchronous
mode or general-purpose I/O port (P45).
• When SCKE = "0" and the DDR4: bit 5 = "0", the SCK functions as serial clock
input.
Bit 0 SOE:
Serial data output bit • This bit selects either serial data output (SO) or general-purpose I/O port (P44).