FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 51)

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CHAPTER 3 CPU
3.4.2 Interrupt Processing
The interrupt controller transmits the interrupt level to the CPU when an interrupt
request is generated by a peripheral function. If the CPU is able to receive the interrupt,
the CPU temporarily halts the currently executing program and executes the interrupt
processing routine.
■ Interrupt processing
The procedure for interrupt operation is performed in the following order: interrupt source generated at
peripheral function, set the interrupt request flag bit (request FF), discriminate the interrupt request enable
bit (enable FF), the interrupt level (ILR1, ILR2, ILR3 and CCR: IL1, IL0), simultaneously generated
interrupt requests with the same level, then check the interrupt enable flag (CCR: I). Figure 3.4-2 "Interrupt
processing" shows the interrupt processing.
Figure 3.4-2 Interrupt processing
START
Initialize peripheral
Is an interrupt
request present at the
peripheral?
Is interrupt
request output enabled
for the peripheral?
Check the interrupt priority level
and transfer the level to the CPU
Compare the level with
the IL bits in PS
Is the level
higher than IL?
I-flag = 1?
Interrupt processing routine
Clear interrupt request
Execute interrupt processing
RETI
Restore PC and PS
Save PC and PS to the stack
PC interrupt vector
Update IL in PS
In
te
rnal
bus
Register
file
IPLA
IR
PS I IL
Condition code
register (CCR)
Check Comparator
Wake-up from
F 2 MC-8L CPU
RAM
(5)
(7)
(6)
(3)
(4)
Enable FF
Request FF
AND
Peripherals
Level com
parat
or
Interrupt
controller
(1)
(3)
(4)
(5)
(7) (6)
YES
YES
YES
YES
NO
NO
NO
NO
stop mode
Wake-up from
sleep mode
Main program
execution
(2)
Exit watch mode