FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 70)

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CHAPTER 3 CPU
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Oscillation stabilization delay time at reset
The oscillation stabilization delay time at reset (the initial values of WT1 and WT0) is selected as an option
setting.
Products with power-on reset require an oscillation stabilization delay time when exit from stop mode is
triggered by resets in power-on reset, or external reset.
Table 3.6-1 "Main clock startup conditions vs. oscillation stabilization delay time" shows the relationships
between the conditions in which main clock mode operation is started and oscillation stabilization delay
time.
Table 3.6-1 Main clock startup conditions vs. oscillation stabilization delay time
Main clock mode startup
conditions
At power-on
Exit from stop mode
External reset External interrupt
Oscillation stabilization delay time
selection
Option setting
With power-on reset
No power-on reset X X
: Oscillation stabilization delay time provided
X: Oscillation stabilization delay time not provided