FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 62)

48
CHAPTER 3 CPU
3.5.3 Pin States during Reset
Reset initializes the pin states.
■ Pin states during reset
When a reset source occurs, with a few exceptions, all I/O pins (peripheral pins) go to the high-impedance
state and the mode data is read from internal ROM (pins with a pull-up resistor (optional) go to the "H"
level).
■ Pin states after reading mode data
With a few exceptions, the I/O pins remain in the high-impedance state immediately after reading the mode
data (pins with a pull-up resistor (optional) go to the "H" level).
Note:
For devices connected to pins that change to high-impedance state when a reset source occurs take care
that malfunction does not occur due to the change in the pin states.
See Appendix E "MB89950/950A Series Pin States" for pin states at the time other than reset.