FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 21)

7
CHAPTER 1 OVERVIEW
1.4 Block Diagram of MB89950/950A Series
Figure 1.4-1 "MB89950/950A series overall block diagram" shows the block diagram of
the MB89950/950A series.
■ MB89950/950A series block diagram
Figure 1.4-1 MB89950/950A series overall block diagram
Main oscillator
circuit
Clock control circuit
Reset circuit
(Watchdog timer)
8-bit PWM timer
Por
t
4
R A M
F 2 MC-8L
CPU
R O M
MODA
V
CC
, V
SS
P41/PWM X0
X1
Int
e
rnal
bus
8-bit
pulse width
count timer
External interrupt
P42/PWC/
INT1
P45/SCK
P44/SO
P43/SI
RST
Noise
filter
8-bit serial I/O
UART
CMOS I/O port
N-ch open-drain I/O port
8
P00/SEG20 to
P07/SEG27
P10/SEG28 to
P17/SEG35
Por
t 0/1/
2
20
SEG0 to
SEG19
COM0 to
COM3
V3
4
LCD controller/driver
P40
P46/INT0
Other pins
8
6
P20/SEG36 to
P25/SEG41
Timebase timer
N-ch open-drain I/O port
Po
rt
3
P30, P31
P33/V2
P32/V1
2
2