FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 61)

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CHAPTER 3 CPU
■ Mode pin
The MB89950/950A series devices are single-chip mode devices. The mode pin (MODA) must be tied to
V
SS
. The mode pin settings determine whether the mode data and reset vector are read from internal ROM.
Do not change the mode pin settings, even after the reset has completed.
■ Mode fetch
When the CPU wakes up from a reset, the CPU reads the mode data and reset vector from internal ROM.
●
Mode data (address: FFFD
H
)
Always set the mode to "00
H
" (single-chip mode).
●
Reset vector (address: FFFE
H
(upper), FFFF
H
(lower))
Contains the address where execution is to start after completion of the reset. The CPU starts executing
instructions from the address contained in the reset vector.
■ Oscillation stabilization delay reset state
On products with power-on reset, the reset operation for a power-on reset or external reset in stop (main
clock) mode starts after the main clock oscillation stabilization delay time selected by the stabilization
delay time option. If the CPU has not woken up from the external reset input when the delay time
completes, the reset operation does not start until the CPU wakes up from external reset.
As the oscillation stabilization delay time is also required when an external clock is used, a reset requires
that the external clock is input.
The main clock oscillation stabilization delay time is timed by the timebase timer.
On products without power-on reset, the oscillation stabilization delay reset state is not used. Therefore, for
such products, hold the external reset pin (RST) at the "L" level to disable the CPU operation until the
source oscillation stabilizes.
■ Effect of reset on RAM contents
The contents of RAM are unchanged before and after a reset other than power-on reset. If an external reset
is input close to a write timing, however, the contents of the write address cannot be assured. For this
reason, all RAM locations being used should be initialized following reset.