FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 120)

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CHAPTER 5 TIMEBASE TIMER
5.4 Timebase Timer Interrupt
The timebase timer can generate an interrupt request when an overflow occurs on the
specified bit of the timebase counter (for the interval timer function).
■ Interrupts for interval timer function
The counter counts up on the internal count clock. When an overflow occurs on the selected interval timer
bit, the overflow interrupt request flag bit (TBTC: TBIF) is set to "1". At this time, an interrupt request
(IRQ6) to the CPU is generated if the interrupt request enable bit is enabled (TBTC: TBIE = "1"). Write "0"
to the TBIF bit in the interrupt processing routine to clear the interrupt request. The TBIF bit is set when at
the specified counter bit overflows, regardless of the TBIE bit value.
Note:
When enabling an interrupt request output (TBIE = "1") after wake-up from a reset, always clear the
TBIF bit (TBIF = "0") at the same time.
References:
• An interrupt request is generated immediately if the TBIF bit is "1" when the TBIE bit is changed from
disabled to enabled ("0" --> "1").
• The TBIF bit is not set if the counter is cleared (TBTC: TBR = "0") at the same time as an overflow on
the specified bit occurs.
■ Oscillation stabilization delay time and timebase timer interrupt
If the interval time is set shorter than the main clock oscillation stabilization delay time, an interval
interrupt request from the timebase timer (TBTC: TBIF = "1") is generated at the time when the clock
mode starts operation. In this case, disable the timebase timer interrupt when entering to a mode in which
the main clock oscillation is stopped (stop mode).
■ Register and vector table for timebase timer interrupts
See Section 3.4.2 "Interrupt Processing" for details on the operation of interrupt.
Table 5.4-1 Register and vector table for timebase timer interrupt
Interrupt
Interrupt level settings register Vector table address
Register Set bit Upper Lower
IRQ6 ILR2 (007D
H
) L61 (Bit 5) L60 (Bit 4) FFEE
H
FFEF
H