FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 130)

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CHAPTER 6 WATCHDOG TIMER
6.4 Operation of Watchdog Timer
The watchdog timer generates a watchdog reset when the watchdog timer counter
overflows.
■ Operation of watchdog timer
●
Activating watchdog timer
The watchdog timer is activated by writing "0101
B
" to the watchdog control bits in the watchdog control
register (WDTC: WTE3 to WTE0) for the first time after a reset.
Once activated, the watchdog timer cannot be stopped other than by a reset.
●
Clearing watchdog timer
The watchdog timer counter is cleared by writing "0101
B
" to the watchdog control bits in the watchdog
control register (WDTC: WTE3 to WTE0) for the second or subsequent times after a reset.
If the counter is not cleared within the interval time of the watchdog timer, the counter overflows and the
watchdog timer generates an internal reset signal for four instruction cycles.
●
Interval time of watchdog timer
The interval time changes depending on when the watchdog timer is cleared.
Figure 6.4-1 "Watchdog timer clear and interval time" shows the relationship between the watchdog timer
clear timing and the interval time.
The indicated times apply if the timebase timer output is selected as the count clock, and the main clock
oscillation frequency is 5 MHz.