FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 52)

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CHAPTER 3 CPU
1. After a reset, all interrupt requests are disabled.
- Initialize the peripheral functions that are to generate interrupts in the peripheral function
initialization program, set the interrupt levels in the appropriate interrupt level setting registers (ILR1,
ILR2, ILR3), and start peripheral function.
- The interrupt level can be set to 1, 2 or 3. Level 1 is the highest priority, followed by level 2. Setting
level 3 disables the interrupt for that peripheral function.
2. Execute the main program (for multiple interrupts, execute the interrupt processing routine).
3. The interrupt request flag bit (request FF) for a peripheral function is set to "1" when the peripheral
function generates an interrupt source. If the interrupt request enable bit for the peripheral function is set
to "enable" (enable FF = "1"), the peripheral function outputs the interrupt request to the interrupt
controller.
4. The interrupt controller continuously monitors for interrupt requests from the peripheral functions and
passes the interrupt level of the current interrupt request with the highest interrupt level to the CPU. The
interrupt controller also evaluates the priority order if requests with the same level are present
simultaneously.
5. If the interrupt level received by the CPU has a higher priority (a lower level value) than the level set in
the interrupt level bits in the condition code register (CCR: IL1, IL0), the CPU checks the interrupt
enable flag (CCR: I) and receives the interrupt if interrupts are enabled (CCR: I = "1").
6. The CPU saves the contents of the program counter (PC) and program status (PS) on the stack, reads the
top address of the interrupt processing routine from the interrupt vector table for the interrupt, updates
the interrupt level bits in the condition code register (CCR: IL1, IL0) with the received interrupt level,
and starts execution of the interrupt processing routine.
7. Finally, on execution of the RETI instruction, the CPU restores the program counter (PC) and program
status (PS) values saved on the stack and resumes execution from the instruction following the last
instruction executed before the interrupt.
Note:
As the interrupt request flag bit of a peripheral function is not cleared automatically when an interrupt
request is received, the bit must be cleared by the program (normally, by writing "0" to the interrupt
request flag bit) at interrupt processing routine.
An interrupt wakes up the CPU from standby mode (low-power consumption). See Section 3.7 "Standby
Modes (Low-power Consumption)" for details.
Reference:
If the interrupt request flag bit is cleared at the top of the interrupt processing routine, the peripheral
function that has generated the interrupt becomes able to generate another interrupt during execution of
the interrupt processing routine (resetting the interrupt request flag bit). However, the interrupts are not
normally accepted until the current processing routine completes.