FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 191)

177
CHAPTER 9 8-BIT SERIAL I/O
Table 9.3-1 Serial mode register (SMR) bits
Bit Function
Bit 7 SIOF:
Interrupt request
flag bit • This bit is set to "1" when the serial output operation has transmitted 8 serial data bits or the serial
input operation has received 8 serial data bits.
An interrupt request is generated when both this bit and the interrupt request enable bit (SIOE) are
"1".
• Writing "0" clears this bit. Writing "1" has no effect and does not change the bit value.
Bit 6 SIOE:
Interrupt request
enable bit This bit enables or disables an interrupt request output to the CPU. An interrupt request is issued
when both this bit and the interrupt request flag bit (SIOF) are "1".
Bit 5 SCKE:
Shift clock output
enable bit • This bit controls shift clock input and output when UART/SIO selection bit (SMC2: RSEL) is set
to "1".
• The P45/SCK pin function as the shift clock input pin when this bit is set to "0" and as the shift
clock output pin when this bit is set to "1".
Notes:
•
Set the P45/SCK pin as an input port when using this pin as the shift clock input. Also, selects
external shift clock operation in the shift clock selection bits (CKS1, CKS0 = "11
B
").
• When using this pin as internal shift clock output (SCK = "1"), select internal shift clock operation
(CKS1, CKS0 = other than "11
B
").
References:
• The pin functions as the SCK output pin when shift clock is enabled (SCKE = "1")
regardless of the state of the general-purpose I/O port (P45).
• Set to shift clock input operation (SCKE = "0") when using this pin as a general-purpose
I/O port (P45).
Bit 4 SOE:
Serial data output
enable bit • This bit controls serial data output when UART/SIO selection bit (SMC2: RSEL) is set to "1".
• The P44/SO pin functions as a general-purpose I/O port (P44) when this bit is set to "0" and as the
serial data output pin (SO) when this bit is set to "1".
Reference:
•
The pin functions as the (SO) pin when serial data output is enabled (SOE = "1"), regardless of the
state of the general-purpose I/O port (P44).
Bit 3
Bit 2 CKS1, CKS0:
Shift clock selection
bits • These bits select the shift clock from one external and three internal shift clocks.
• Setting these bits to other than "11
B
" selects an internal shift clock. In this case, the shift
clock is output from the SCK pin if the shift clock output enable bit (SCKE) is "1".
• Setting these bits to "11
B
" selects the external shift clock. This inputs the shift clock
from the SCK pin if shift clock input is enabled (SCKE = "0" and DDR4: bit 5 = "0").
Bit 1 BDS:
Transfer direction
selection bit • This bit selects whether serial data is transferred with the least significant bit first (LSB
first, BDS = "0") or the most significant bit first (MSB first, BDS = "1").
Note:
• As bits are set in the appropriate order when writing to or reading from the serial data
register (SDR), modifying this bit does not apply to any data already set in the SDR
register.