FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 233)

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CHAPTER 10 UART
Figure 10.7-3 Receive operation in mode 0, 1, 3
Figure 10.7-4 Operation at overrun error in mode 0, 1, 3
Figure 10.7-5 Operation at framing error in mode 0, 1, 3
Reference:
When the system wakes up from the initialize process caused by reset, an initializing period of 11 shift
clocks is needed for initializing the internal control blocks.
Data
RDRF
Receive interrupt
START 0 1 2 3 4 5 6 7 STOP 8
Data
ORFE
RDRF=1
(Receive buffer full)
Receive interrupt
START 0 1 2 3 4 5 6 7 STOP 8
Data
ORFE
Receive interrupt
START 0 1 2 3 4 5 6 7 STOP 8
RDRF=0