FUJITSU Semiconductor Controller MB89950/950A - Manual (Page 145)

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CHAPTER 7 8-BIT PWM TIMER
7.4 8-bit PWM Timer Interrupts
The 8-bit PWM timer can generate an interrupt request when a match is detected
between the counter value and PWM compare register value for the interval timer
function. Interrupt requests are not generated for the PWM timer function.
8-bit PWM timer generates the IRQ2 as an interrupt request.
■ Interrupts for interval timer function
The counter starts to count up from "00
H
" on the selected count clock. When the counter value matches the
PWM compare register (COMR) value, the interrupt request flag bit (CNTR: TIR) is set to "1".
At this time, an interrupt request (IRQ2) to the CPU is generated if the interrupt request enable bit is
enabled (CNTR: TIE = "1"). Write "0" to the TIR bit in the interrupt processing routine to clear the
interrupt request.
The TIR bit is set to "1" when the counter value matches the set value, regardless of the value of the TIE
bit.
Reference:
The TIR bit is not set if the counter is stopped (CNTR: TPE = "0") at the same time as the counter value
matches the COMR register value.
An interrupt request is generated immediately if the TIR bit is "1" when the TIE bit is changed from
disabled to enabled ("0" --> "1").
■ Registers and vector tables for 8-bit PWM timer interrupts
See Section 3.4.2 "Interrupt Processing" for details on the interrupt operation.
Table 7.4-1 Registers and vector tables for 8-bit PWM timer interrupts
Interrupt
Interrupt level setting register Vector table address
Register Setting bits Upper Lower
8-bit PWM timer IRQ2 ILR1 (007C
H
) L21 (Bit 5) L20 (Bit 4) FFF6
H
FFF7
H