Cirrus Logic CS42L73 - Manual (Page 10)

10 DS882F1
CS42L73
Figure 27.I²S Format ................................................................................................................................. 55
Figure 28.PCM Format—Mode 0 .............................................................................................................. 56
Figure 29.PCM Format—Mode 1 .............................................................................................................. 56
Figure 30.PCM Format—Mode 2 .............................................................................................................. 57
Figure 31.Digital Mic Interface Signaling ................................................................................................... 60
Figure 32.Digital Mixer Diagram ................................................................................................................ 62
Figure 33.Connection Diagram for Using MIC2_SDET as Headphone Detect ......................................... 69
Figure 34.Flow Diagram Showing the INT Pin State in Response to MIC2_SDET State Changes .......... 69
Figure 35.Connection Diagram for Headphone Detect with Additional Short Detect ................................ 70
Figure 36.Example of Rising-Edge Sensitive, Sticky, Interrupt Status Bit Behavior ................................. 71
Figure 37.Control Port Timing, I²C Writes with Autoincrement ................................................................. 72
Figure 38.Control Port Timing, I²C Reads with Autoincrement ................................................................. 72
Figure 39.Control Port Timing, I²C Reads with Preamble and Autoincrement .......................................... 73
Figure 40.Fast Start Pop ........................................................................................................................... 74
Figure 41.Start Up Transition Diagram ..................................................................................................... 75
Figure 42.PGA DNL ................................................................................................................................ 126
Figure 43.PGA INL .................................................................................................................................. 126
Figure 44.PGA + Preamp (+10 dB) DNL ................................................................................................. 126
Figure 45.PGA + Preamp (+10 dB) INL .................................................................................................. 126
Figure 46.PGA + Preamp (+20 dB) DNL ................................................................................................. 127
Figure 47.PGA + Preamp (+20 dB) INL .................................................................................................. 127
Figure 48.Input Path LPF Frequency Response ..................................................................................... 127
Figure 49.Input Path LPF Stopband Rejection ........................................................................................ 127
Figure 50.Input Path LPF Transition Band .............................................................................................. 128
Figure 51.Input Path LPF Transition Band Detail .................................................................................... 128
Figure 52.Input Path HPF Frequency Response .................................................................................... 128
Figure 53.ASRC Frequency Response ................................................................................................... 129
Figure 54.ASRC Passband Frequency Response .................................................................................. 129
Figure 55.ASRC Group Delay vs. Serial Port and Internal Sample Rates .............................................. 130
Figure 56.DAC LPF Frequency Response .............................................................................................. 131
Figure 57.DAC LPF Stopband Rejection to 1x Fs ................................................................................... 131
Figure 58.DAC LPF Stopband Rejection to 3x Fs ................................................................................... 131
Figure 59.DAC HPF Frequency Response ............................................................................................. 132
Figure 60.HPOUTx DNL (-50 to +12 dB) ................................................................................................ 132
Figure 61.HPOUTx DNL (-76 to -52 dB) ................................................................................................. 132
Figure 62.HPOUTx INL (-50 to +12 dB) .................................................................................................. 132
Figure 63.HPOUTx INL (-76 to -52 dB) ................................................................................................... 132
Figure 64.LINEOUTx DNL (-50 to +12 dB) ............................................................................................. 133
Figure 65.LINEOUTx DNL (-76 to -52 dB) .............................................................................................. 133
Figure 66.LINEOUTx INL (-50 to +12 dB) ............................................................................................... 133
Figure 67.LINEOUTx INL (-76 to -52 dB) ................................................................................................ 133
LIST OF TABLES
Table 1. Internal Master Clock Generation ............................................................................................... 42
Table 2. Example of Impedance in Reference Path .................................................................................. 44
Table 3. Current through VCP with Varying Short Circuits ....................................................................... 51
Table 4. Supported MCLK1/MCLK2 Rates for Pre-MCLK Mode .............................................................. 53
Table 5. Serial Port Rates and Master Mode Settings .............................................................................. 53
Table 6. Actual xSP_LRCK Rate/Deviation Selector for
Note 3 ............................................................... 54
Table 7. Supported Serial Port Formats .................................................................................................... 54
Table 8. Input Path Source Select and Digital Power States .................................................................... 59
Table 9. Digital Mic Interface Power States .............................................................................................. 60
Table 10. Digital Microphone Interface Clock Generation ......................................................................... 61