Cirrus Logic CS42L73 - Manual (Page 4)

4 DS882F1
CS42L73
TABLE OF CONTENTS
1. PACKAGE PIN/BALL ASSIGNMENTS AND CONFIGURATIONS ..................................................... 12
1.1 64-Ball Wafer-Level Chip Scale Package (WLCSP) ...................................................................... 12
1.2 65-Ball Fine-Pitch Ball Grid Array (FBGA) Package ...................................................................... 13
1.3 Pin/Ball Descriptions ...................................................................................................................... 14
1.4 Digital Pin/Ball I/O Configurations .................................................................................................. 16
2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 17
2.1 Low-Profile Charge-Pump Capacitors ........................................................................................... 18
2.2 Ceramic Capacitor Derating ........................................................................................................... 18
3. CHARACTERISTIC AND SPECIFICATIONS ...................................................................................... 19
4. APPLICATIONS ................................................................................................................................... 41
4.1 Overview ........................................................................................................................................ 41
4.1.1 Basic Architecture ................................................................................................................. 41
4.1.2 Line and Microphone Inputs .................................................................................................. 41
4.1.3 Line and Headphone Outputs (Class H, Ground-Centered Amplifiers) ................................. 41
4.1.4 Digital Mixer ........................................................................................................................... 41
4.1.5 Power Management .............................................................................................................. 41
4.2 Internal Master Clock Generation .................................................................................................. 42
4.3 Thermal Overload Notification ....................................................................................................... 42
4.4 Pseudodifferential Outputs ............................................................................................................. 43
4.5 Class H Amplifier .......................................................................................................................... 44
4.5.1 Power Control Options .......................................................................................................... 44
4.5.1.1 Standard Class AB Operation (Mode 001, 010, and 011) ......................................... 45
4.5.1.2 Adapt-to-Volume Settings (Mode 000) ...................................................................... 45
4.5.1.3 Adapt-to-Output Signal (Mode 111) ........................................................................... 46
4.5.2 Power Supply Transitions ...................................................................................................... 46
4.5.3 Efficiency ............................................................................................................................... 49
4.6 DAC Limiter .................................................................................................................................... 49
4.7 Analog Output Current Limiter ....................................................................................................... 51
4.8 Serial Ports .................................................................................................................................... 51
4.8.1 Power Management .............................................................................................................. 51
4.8.2 I/O .......................................................................................................................................... 51
4.8.3 High-impedance Mode .......................................................................................................... 52
4.8.4 Master and Slave Timing ....................................................................................................... 52
4.8.4.1 SCLK = MCLK Modes ............................................................................................... 53
4.8.5 Serial Port Sample Rates and Master Mode Settings ........................................................... 53
4.8.6 Formats ................................................................................................................................. 54
4.8.6.1 I²S Format .................................................................................................................. 55
4.8.6.2 PCM Format .............................................................................................................. 55
4.8.7 Mono/Stereo .......................................................................................................................... 57
4.8.8 Data Bit Depths ..................................................................................................................... 57
4.8.8.1 I²S Format Bit Depths ................................................................................................ 57
4.8.8.2 PCM Format Bit Depths ............................................................................................. 58
4.9 Asynchronous Sample Rate Converters (ASRCs) ......................................................................... 59
4.10 Input Paths ................................................................................................................................... 59
4.10.1 Input Path Source Selection and Powering ......................................................................... 59
4.10.2 Digital Microphone (DMIC) Interface ................................................................................... 60
4.10.2.1 DMIC Interface Description ...................................................................................... 60
4.10.2.2 DMIC Interface Signaling ......................................................................................... 60
4.10.2.3 DMIC Interface Powering ......................................................................................... 60
4.10.2.4 DMIC Interface Clock Generation ............................................................................ 61
4.11 Digital Mixer ................................................................................................................................. 61
4.11.1 Mono and Stereo Paths ....................................................................................................... 63