Cirrus Logic CS42L73 - Manual (Page 28)

28 DS882F1
CS42L73
Notes:
30. Analog Gain setting (refer to “Headphone x Analog Volume Control” on page 103 or “Line Output x Analog Volume Con-
trol” on page 104 ) must be configured as indicated to achieve specified output characteristics.
31. If the VCP supply level is less than the VA supply level, clipping may occur as the audio signal is handed from the VA
to the VCP powered circuits in the output amplifier. This clipping would occur as the audio signal approaches full-scale,
maximum power output and could prevent achievement of THD+N performance.
32. Full-scale output voltage and power are determined by analog gain settings. Full-scale output voltage values here refer
to the maximum voltage difference achievable on the analog output pins, measured between the HPOUTx/LINEOUTx
and HPOUT_REF/LINEO_REF pins. Modifying internal gain settings to increase peak-to-peak voltage may cause an-
alog output signal clipping, degrading THD+N performance.
33. Unless otherwise specified, measurement is taken for each load resistance test case with the gain set as indicated for
the dynamic range, etc., performance specifications at the given load resistances.
34. Measured between stereo pairs (HPOUTA to HPOUTB or LINEOUTA to LINEOUTB).
35.
Figure 5 on page 28 and Figure 6 on page 29 shows headphone and line output test configurations.
36. Valid with the recommended capacitor values on FILT+ and ANA_VQ. Increasing capacitance on FILT+ and ANA_VQ
increases the PSRR at low frequencies.
37. High-impedance state enabled as described in Section 4.18 .
Full-scale Output Voltage (Note 32) 1.56•VA 1.64•VA 1.73•VA V
PP
Other Characteristics for R
L
= 16  , 32 or 3 k (Note 33)
Interchannel Isolation (Note 34) - 90 - dB
Interchannel Gain Mismatch (Note 34) - ±0.1 ±0.25 dB
Output Offset Voltage (DAC to HPOUTx) Analog mute enabled
0 dB analog gain
-
- ±0.1
±0.3 ±1.0
±2.0 mV
mV
Gain Drift - ±100 - ppm/°C
Load Resistance (R
L
) (Note 35) 16 - - 
Load Capacitance (C
L
) (Note 35) - - 150 pF
PSRR with 100 mV
PP
signal AC-coupled to VA supply 217 Hz
- Analog Gain = 0 dB; Input test signal held low (all zeros data) 1 kHz
(Note 8) (Note 36) 20 kHz
-
-
- 75
75
70 -
-
- dB
dB
dB
PSRR with 100 mV
PP
signal AC-coupled to VCP supply 217 Hz
- Analog Gain = 0 dB; Input test signal held low (all zeros data) 1 kHz
(Note 8) (Note 36) 20 kHz
-
-
- 85
85
70 -
-
- dB
dB
dB
Output Impedance High-Impedance Mode (Note 37) 3.0 3.14 - k 
SERIAL PORT TO STEREO HP OUTPUT CHARACTERISTICS (CONTINUED)
Test conditions (unless otherwise specified): “Typical Connection Diagram” on page 17 shows CS42L73 connections (including
Zobel Networks on outputs); Input test signal is a 24-bit full-scale 997-Hz sine wave with 1 LSB of triangular PDF dither applied;
GND = AGND = PGND = CPGND = DGND = 0 V; all voltages are with respect to ground (GND); VA = VCP = 1.80 V; T
A
= +25
C; VCP Mode; Measurement Bandwidth is 20 Hz to 20 kHz; Fs = 48 kHz (Note 10) ; ASP is used and is in slave mode with Fs
ext
= 48 kHz; test loading is configured as per Figure 5 on page 28 (R
L
and C
L
(= C
L(Max)
) as indicated in the table below); Mixer
Attenuation and Digital Volume = 0 dB, Digital and Analog Mutes are disabled.
Parameters (Note 2) Min Typ Max Units
Zobel
Network
Test Load
HPOUTx
CPGND/AGND
C
L
33 nF
100 
HPOUT_REF
R
L Measurement
Device
-
+
Figure 5. Headphone Output Test Configuration