Cirrus Logic CS42L73 - Manual (Page 38)

38 DS882F1
CS42L73
SWITCHING SPECIFICATIONS—SERIAL PORTS—I²S FORMAT
Test conditions: Inputs: Logic 0 = GND = DGND = 0 V, Logic 1 = VL; T
A
= +25 C; x = X, A, or V; xSP_LRCK, xSP_SCLK, xSP_
SDOUT; C
LOAD
= 15 pF.
Notes:
56. In Master Mode, the output sample rate follows the Master Clock source (MCLK1 or MCLK2) rate divided down per “In-
ternal Master Clock Generation” on page 42 and “Serial Port Sample Rates and Master Mode Settings” on page 53 .
Any Master Clock source deviation from the nominal supported rates is directly imparted to the output sample rate by
the same factor (e.g., +100 ppm offset in the MCLK1/MCLK2 frequency becomes a +100 ppm xSP_LRCK offset).
57. Maximum frequency for highest supported nominal rate is indicated. The supported nominal rates are described in sec-
tion “SCLK = MCLK Modes” on page 53 .
Parameters (Note 2) Symbol Min Max Units
Slave Mode
Input sample Rate (xSP_LRCK)
(Note 24) (Note 53) Fs
ext-s
- 50 kHz
xSP_LRCK Duty Cycle - 45 55 %
xSP_SCLK Frequency (Note 10) 1/t
Ps
- 68•Fs Hz
xSP_SCLK Duty Cycle - 45 55 %
xSP_LRCK Setup Time Before xSP_SCLK Rising Edge t
ss(LK-SK)
40 - ns
xSP_LRCK Hold Time After xSP_SCLK Rising Edge t
hs(SK-LK)
20 - ns
xSP_SDOUT Setup Time Before xSP_SCLK Rising Edge t
ss(SDO-SK)
20 - ns
xSP_SDOUT Hold Time After xSP_SCLK Rising Edge t
hs(SK-SDO)
30 - ns
xSP_SDIN Setup Time Before xSP_SCLK Rising Edge t
ss(SDI-SK)
20 - ns
xSP_SDIN Hold Time After xSP_SCLK Rising Edge t
hs(SK-SDI)
20 - ns
Master Mode
Output Sample Rate (xSP_LRCK)
(Note 24) Fs
ext-m
- (Note 56) kHz
xSP_LRCK Duty Cycle - 45 55 %
xSP_SCLK Frequency “SCLK  MCLK” Mode
“SCLK = MCLK” Mode
“SCLK = Pre-MCLK” Mode (Note 57)
1/t
Pm
-
-
- 68•Fs
ext-m
MCLK
12.1
Hz
Hz
MHz
xSP_SCLK Duty Cycle - 45 55 %
xSP_LRCK Setup Time Before xSP_SCLK Rising Edge t
sm(LK-SK)
35 - ns
xSP_LRCK Hold Time After xSP_SCLK Rising Edge t
hm(SK-LK)
20 - ns
xSP_SDOUT Setup Time Before xSP_SCLK Rising Edge t
sm(SDO-SK)
20 - ns
xSP_SDOUT Hold Time After xSP_SCLK Rising Edge t
hm(SK-SDO)
30 - ns
xSP_SDIN Setup Time Before xSP_SCLK Rising Edge t
sm(SDI-SK)
20 - ns
xSP_SDIN Hold Time After xSP_SCLK Rising Edge t
hm(SK-SDI)
20 - ns
t
h (SK-SDO)
//
t
s (SDI-SK)
xSP_LRCK
xSP_SCLK
xSP_SDOUT
xSP_SDIN
t
P 
t
h (SK-SDI)
t
s (SDO-SK)
Note:
x = X, A, or V;
 = “s” or “m”
t
s (LK-SK)
t
h (SK-LK)
Figure 12. Serial Port Interface Timing—I²S Format