Cirrus Logic CS42L73 - Manual (Page 31)

DS882F1 31
CS42L73
SERIAL PORT-TO-MONO SPEAKERPHONE OUTPUT CHARACTERISTICS
Test conditions (unless otherwise specified): “Typical Connection Diagram” on page 17 shows CS42L73 connections; Input test
signal is a 24-bit full-scale 997 Hz sine wave with 1 LSB of triangular PDF dither applied; GND = AGND = PGND = CPGND =
DGND = 0 V; all voltages are with respect to ground (GND); VA = 1.80 V, VP = 3.70 V; T
A
= +25 C; Measurement Bandwidth is
20 Hz to 20 kHz; Fs = 48 kHz (Note 10) ; ASP is used and is in slave mode with Fs
ext
= 48 kHz; test loading is configured as per
Figure 8 on page 32 (R
L
, C
L1
(= C
L1(Max)
) and C
L2
(= C
L2(Max)
) as indicated in the table below); Mixer Attenuation = 0 dB, Digital
Volume = -5.5 dB, Digital Mute is disabled, SPK_LITE_LOAD = 0b and 1b for R
L
= 8  and 50 krespectively.
Notes:
42. When the VP supply level is low and the VA supply level is high, clipping may occur as the audio signal is handed off
from the VA to the VP powered circuits within the output amplifier. This clipping would occur as the audio signal ap-
proached full-scale, maximum power output and could result in the specified THD+N performance not being achieved.
43. The maximum speakerphone capacitance across the load is specified as C
L1
. If more load capacitance is desired, con-
tact Cirrus Logic for alternatives using additional external circuitry.
44. Valid with the recommended capacitor values on FILT+ and SPK_VQ. Increasing the capacitance on FILT+ and SPK_
VQ will increase the PSRR at low frequencies.
Parameters (Note 2) Min Typ Max Units
Load R
L
= 8 (SPK_LITE_LOAD = 0)
Dynamic Range
16 to 24-Bit
A-weighted
unweighted
80
77 86
83 -
- dB
dB
Total Harmonic Distortion + Noise (Note 39) (Note 42) , 16- to 24-Bit
0 dBFS, P
OUT
= 0.48 W -
- -65
0.056
-62
0.079
dB
%
Full-scale Output Voltage (Note 39) (Diff. SPKOUT ±, see Note 40 ) 2.85•VA 3.09•VA 3.33•VA V
PP
Output Power (P
OUT
) (Continuous Average) (Note 39)
THD+N  -62 dB (0.079%) VP = 3.70 V, Dig. Vol. = -5.5 dB
THD+N  -40 dB (1.0%) VP = 3.70 V, Dig. Vol. = -4.5 dB
VP = 4.20 V, Dig. Vol. = -3.5 dB
VP = 5.00 V, Dig. Vol. = -2.0 dB
THD+N  -20 dB (10%) VP = 3.70 V, Dig. Vol. = -2.5 dB
VP = 4.20 V, Dig. Vol. = -1.5 dB
VP = 5.00 V, Dig. Vol. = 0.0 dB
-
-
-
-
-
-
- 0.48
0.59
0.76
1.06
0.75
0.95
1.36 -
-
-
-
-
-
- W
W
W
W
W
W
W
Load R
L
= 50 k (SPK_LITE_LOAD = 1)
Dynamic Range
16 to 24-Bit
A-weighted
unweighted
78
75 84
81 -
- dB
dB
Total Harmonic Distortion + Noise (Note 39) (Note 42) 16 to 24-Bit 0 dBFS - -65 -60 dB
Full-scale Output Voltage (Note 39) (Diff. SPKOUT ±, see Note 40 ) 2.99•VA 3.23•VA 3.47•VA V
PP
Other Characteristics for R
L
= 8  or 50 k (Note 33)
Output Offset Voltage (DC offset of diff. SPKOUT ±, see Note 40 ) - ±5.0 ±10.0 mV
Gain Drift - ±100 - ppm/°C
Load Resistance (R
L
) (Note 41) SPK_LITE_LOAD = 0b
SPK_LITE_LOAD = 1b 6.5
3.0 8
50
100
-

k 
Load Capacitances C
L1
across outputs/load
(Note 41) (Note 43) C
L2
from each output to ground
-
- -
- 150
50
pF
pF
PSRR with 100 mV
PP
signal AC-coupled to VA supply 217 Hz
- Input test signal held low (all zeros data) 1 kHz
(Note 36) 20 kHz
-
-
- 70
70
70 -
-
- dB
dB
dB
PSRR with 100 mV
PP
signal AC-coupled to VP supply 217 Hz
- Input test signal held low (all zeros data) 1 kHz
(Note 44) 20 kHz
-
-
- 70
80
60 -
-
- dB
dB
dB