Cirrus Logic CS42L73 - Manual (Page 43)

DS882F1 43
CS42L73
4.4 Pseudodifferential Outputs
The CS42L73 provides access to the headphone and line output amplifiers’ reference inputs via the
HPOUT_REF and LINEO_REF pins. These pins may be connected to either the ground at the device, or
the ground return pin of each amplifier’s corresponding output connector. By routing HPOUT_REF and
LINEO_REF to the ground at the device, the respective amplifier’s common mode is dictated by the
ground local to the device. An equivalent circuit is shown in
Figure 15 where the ground-noise voltages
developed local to the device and the jack are modeled as voltage sources V
N-LOCAL
and V
N-JACK
, re-
spectively. V
N-LOCAL
is transferred to the output of the amplifier. V
N-LOCAL
- V
N-JACK
is then presented
across the load (V
N-LOAD
). For PCB designs in which the headphone or line output signals traverse long
distances to an output connector, V
N-LOCAL
and V
N-JACK
can be different. As such, V
N-LOAD
may be sig-
nificant and can compromise dynamic range performance.
By routing HPOUT_REF and LINEO_REF to the corresponding output connector as shown in Figure 16 ,
however, the amplifier’s common mode is dictated by the ground local to the jack. This connection is use-
ful in systems for which, as described above, the ground noise local to the device differs from the ground
noise at the jack. As this noise voltage couples to HPOUT_REF and LINEO_REF, it is also transferred
through the amplifier to its output. This behavior allows the ground noise at the jack to be seen as common
mode at the load, and as a result, V
N-LOAD
is minimized.
Minimize any impedance from the HPOUT_REF and LINEO_REF pins to the corresponding load ground
(typically the connector ground). Impedance in this path affects analog output attenuation of the output
amplifier, which affects output offset and step deviation.
Table 2 shows the effects of impedance on the
reference pin with regard to output attenuation:
V
N-LOCAL
V
N-JACK
PGND/DGND/CPGND/AGND
PCB
CS42L73
JACK
LOAD
≈ V
N-LOCAL
V
N-LOAD
≈ V
N-LOCAL
- V
N-JACK
HPOUT_REF
LINEO_REF
HPOUTx
LINEOUTx
Figure 15. Single-Ended Output Configuration
V
N-JACK
GNDD/GNDA/GNDCP
PCB
CS42L73
JACK
LOAD
≈ V
N-JACK
V
N-LOAD
≈ 0
HPOUT_REF
LINEO_REF
HPOUTx
LINEOUTA
LINEOUTB
Figure 16. Pseudodifferential Output Configuration